at96.v

isa总线接口

`timescale 1 ns / 1 ns
module at96(	clk,rst,
				ior,iow,memr,memw,bus_data,bus_addr,aen,					//at96 bus sig
				doe,dir,												//4245 control sig
				av_rd,av_bus_data,av_bus_addr,							//a type monitor interface sig
				tvchk_bus_data,											//tv check sig
				tv_irda_alter_data,										//tv irda alternate sig
				flash_addr,flash_data,flash_ce,flash_oe,flash_we,		//zhiku flash interface sig
				ad_a_data,ad_b_data,ad_c_data,							//stick ad sample data
				sw_data,												//switch input
				wd_data,												//watch dog io register
				flash_state,
				dis_switch);
				
//system clk and reset signal
input clk;									//40m
input rst;

//the next port declaration is the isa_bus signal
input ior;									//at96 bus io read strobe sig
input iow;									//at96 bus io write strobe sig
input memr;									//at96 bus memory read strobe
input memw;									//at96 bus memroy write strobe
input aen;									//at96 bus dma operation strobe
inout [7:0] bus_data;						//at96 data bus
input [23:0] bus_addr;						//at96 address bus


//4245 control signal
output doe;									//4245 oe sig
output dir;									//4245 director sig
	
//a type display dram interface signal
output av_rd;							//a type monitor dram read strobe
output [11:0] av_bus_addr;				//a type monitor dram address bus
input [7:0] av_bus_data;				//a type monitor dram data bus

//tv check data input 
input [7:0] tvchk_bus_data;				//tv check data input io reg

//tv irda alternate output control word
output [7:0] tv_irda_alter_data;		//tv irda alternate output io reg

//switch input register 
input [7:0] sw_data;

//flash state io register
input [7:0] flash_state;

//watch dog out io register
output [7:0] wd_data;
reg [7:0] wd_data;

//zhiku flash operation port
output [19:0] flash_addr;				//flash address bus
inout [7:0] flash_data;					//flash data bus
output flash_ce;						//flash chip select
output flash_oe;						//flash read strobe
output flash_we;						//flash write strobe

//stick ad sample data input port
input [7:0] ad_a_data;					//8255 a port,input
input [7:0] ad_b_data;					//8255 b port,input
input [7:0] ad_c_data;					//8255 c port,input

//display switch
output [2:0] dis_switch;
reg [7:0] dis_switch_reg;

//chip selce sig
wire cs_w;								//chip write strobe, used to strobe the input of the bidir bus(at96)
wire cs;								//chip select, used to strobe the 4245 (at96)
wire cs_r;								//chip read strobe, used to strobe the output of the bidir bus(at96)
wire [2:0] out_sel;						//output mux select of the bidir bus(at96)

//at 96 bidir data bus mux and demux
reg [7:0] out_reg;						//at 96 bidir data bus output mux
wire [7:0] in_reg;						//at 96 bidir data bus input demux

//a type video reg
wire [7:0] av_mem_addr;					
reg av_rd;
reg av_cs;
reg [7:0] addr_ena;
wire av_ena;
reg memr1,memr2;

//tv check reg signal
							
wire [9:0] io_cs_addr;					//io chip select address, 10 bit, a[9..0]

//tv irda reg signal
					
wire tv_irda_wr;

reg [7:0] tv_irda_alter_data;

//flash reg signal
reg flash_ce_reg;
reg zhiku_w_cs;
reg zhiku_r_cs;
wire [4:0] flash_cs_addr;
reg [7:0] flash_we_reg;
wire flash_wr_ena;

reg [7:0] exp_addr_data;
wire [7:0] zhiku_data;

//io reg 
reg io_we;							//io register write strobe
reg io_oe;							//io register read strobe
wire mem_we;						//memory write strobe
reg [7:0] io_data;					//io register

reg ior1,ior2;



//chip select address
parameter av_cs_addr 			= 8'he6;		//a type monitor dram address space
parameter tvchk_cs_addr 		= 10'h388;		//tv check io register  address space
parameter tv_irda_alter_addr 	= 10'h38b;		//tv irda alternate io register address space
parameter zhiku_addr 			= 5'b11010;		//zhiku flash  address space
parameter exp_cs_addr		 	= 10'h2f7;		//zhiku expandation address io register  address space
parameter ad_8255_a		 		= 10'h240;		//8255 a port io register address space
parameter ad_8255_b		 		= 10'h241;		//8255 b port io register address space
parameter ad_8255_c		 		= 10'h242;		//8255 c port io register address space
parameter sw_addr				= 10'h384;		//swith input register(read only)
parameter wd_addr				= 10'h383;		//watch dog io register (write only)
parameter flash_state_addr		= 10'h382;		//flash state io register address
parameter addr_ena_addr			= 10'h389;		//av_addr encode enable io register address
parameter dis_switch_addr		= 10'h38a;		//dis_switch encode enable io register address
parameter flash_we_addr			= 10'h381;		//dis_switch encode enable io register address


/*initial 
begin
	av_rd=0;
	av_cs=0;

	out_reg=8'b0;
	tv_irda_alter_wr=0;
	zhiku_r_cs=0;
	io_oe=0;
	io_we=0;
end*/

//io reg write operation
assign io_cs_addr = bus_addr[9:0];	
assign dis_switch = dis_switch_reg[2:0];		

always @(io_cs_addr or iow or aen)			
begin
	if(aen==0 && iow==0)
		case(io_cs_addr)
		tv_irda_alter_addr	:io_we<=1;
		exp_cs_addr			:io_we<=1;
		wd_addr				:io_we<=1;
		addr_ena_addr		:io_we<=1;
		dis_switch_addr		:io_we<=1;
		flash_we_addr		:io_we<=1;
		default				:io_we<=0;
		endcase
	else
		io_we<=0;
end

always @(negedge rst or posedge iow)
begin
	if(rst==0)
		begin
			tv_irda_alter_data<=8'b0;
			exp_addr_data<=8'b0;
			wd_data<=8'b0;
			addr_ena<=8'b0;
			dis_switch_reg<=8'b0;
			flash_we_reg<=8'b0;
		end
	else if(aen==0)
		case(io_cs_addr)
		tv_irda_alter_addr	:tv_irda_alter_data<=in_reg;
		exp_cs_addr			:exp_addr_data<=in_reg;
		wd_addr				:wd_data<=in_reg;
		addr_ena_addr		:addr_ena<=in_reg;
		dis_switch_addr		:dis_switch_reg<=in_reg;
		flash_we_addr		:flash_we_reg<=in_reg;
		endcase
end

//ior_reg signal generate
always @(negedge rst or negedge clk)
begin
	if(rst==0)
		begin
			ior1<=0;
			ior2<=0;
		end
	else
		begin
			ior1<=ior;
			ior2<=ior1;
		end
end

always @(negedge rst or negedge clk)
begin
	if(rst==0)
		begin
			io_oe <= 0;
		end
	else	if(!ior1 && ior2)
				begin
					if(aen==0)
						case(io_cs_addr)
							tvchk_cs_addr		:io_oe<=1;
							ad_8255_a			:io_oe<=1;
							ad_8255_b			:io_oe<=1;
							ad_8255_c			:io_oe<=1;
							sw_addr				:io_oe<=1;
							flash_state_addr	:io_oe<=1;
							dis_switch_addr		:io_oe<=1;
							addr_ena_addr		:io_oe<=1;
							default				:io_oe<=0;
						endcase
					else
						begin
							io_oe<=0;
						end
				end
				//ior_reg<=1;
			else if(ior1 && !ior2)
					begin
						io_oe<=0;	
					end
end

always @(negedge rst or negedge clk)
begin
	if(rst==0)
		begin
			io_data<=8'b1;
		end
	else	if(!ior1 && ior2)
				begin
					if(aen==0)
						case(io_cs_addr)
							tvchk_cs_addr		:io_data<=tvchk_bus_data;
							ad_8255_a			:io_data<=ad_a_data;
							ad_8255_b			:io_data<=ad_b_data;
							ad_8255_c			:io_data<=ad_c_data;
							sw_addr				:io_data<=sw_data;
							flash_state_addr	:io_data<=flash_state;
							dis_switch_addr		:io_data<=dis_switch_reg;
							addr_ena_addr		:io_data<=addr_ena;
							default				:io_data<=8'b1;
						endcase
					else
						begin
							io_data<=8'b1;
						end
				end
				//ior_reg<=1;
			else if(ior1 && !ior2)
					begin
						io_data<=8'b1;
					end
end


//io reg read operation
/*always @(io_cs_addr or ior_reg or aen)
begin
	if(aen==0 && ior_reg==1)
		case(io_cs_addr)
		tvchk_cs_addr		:io_oe<=1;
		ad_8255_a			:io_oe<=1;
		ad_8255_b			:io_oe<=1;
		ad_8255_c			:io_oe<=1;
		default				:io_oe<=0;
		endcase
	else
		begin
			io_oe<=0;
		end
end

always @(posedge ior_reg)
begin
	if(aen==0)
		case(io_cs_addr)
			tvchk_cs_addr		:io_data<=tvchk_bus_data;
			ad_8255_a			:io_data<=ad_a_data;
			ad_8255_b			:io_data<=ad_b_data;
			ad_8255_c			:io_data<=ad_c_data;
			default				:io_data<=8'b1;
		endcase
end*/

//a type monitor decoder
assign av_bus_addr = bus_addr[11:0];

assign av_mem_addr = bus_addr[19:12];

assign av_ena = addr_ena[0];

always @(negedge rst or negedge clk)
begin
	if(rst==0)
		begin
			memr1<=1;
			memr2<=1;
		end
	else
		begin
			memr1<=memr;
			memr2<=memr1;
		end
end

always @(negedge rst or negedge clk)
begin
	if(rst==0)
		begin
			av_rd<=0;
			av_cs<=0;
		end
	else	if(!memr1 && memr2)
				begin
					if(av_mem_addr==av_cs_addr && aen==0 && av_ena)
						begin
							av_rd<=1;
							av_cs<=1;

						end
					else
						begin
							av_rd<=0;
							av_cs<=0;
						end
				end
			else if(memr1 && !memr2)
					begin
						av_rd<=0;
						av_cs<=0;
					end
end

/*always @(av_mem_addr or av_rd or aen)
begin
	if(av_mem_addr==av_cs_addr && av_rd==1 && aen==0)
		begin
			//av_rd<=1;
			av_cs<=1;
		end
	else
		begin
			//av_rd<=0;
			av_cs<=0;
		end
end*/

/**************flash begin*******************/
assign flash_cs_addr = bus_addr[19:15];

assign flash_wr_ena = flash_we_reg[0];

always @(flash_cs_addr or aen)
begin
	if(flash_cs_addr==zhiku_addr && aen==0)
		flash_ce_reg<=1;
	else 
		flash_ce_reg<=0;
end

assign flash_ce = !flash_ce_reg;

always @(flash_cs_addr or memw or aen)
begin
	if(flash_cs_addr==zhiku_addr && memw==0 && aen==0)
		zhiku_w_cs<=1;
	else 
		zhiku_w_cs<=0;
end

always @(flash_cs_addr or memr or aen)
begin
	if(flash_cs_addr==zhiku_addr && memr==0 && aen==0)
		zhiku_r_cs<=1;
	else 
		zhiku_r_cs<=0;
end

assign flash_oe = memr;
assign flash_we = flash_wr_ena?memw:1;

assign flash_addr = {exp_addr_data[4:0],bus_addr[14:0]};

assign flash_data = zhiku_w_cs?in_reg:8'bz;
assign zhiku_data = zhiku_r_cs?flash_data:zhiku_data;
/**************flash        end**************/



/******data bus output port begin*********/
assign bus_data = cs_r?out_reg:8'bz;

always @(out_sel or av_bus_data or io_data or zhiku_data)
begin
	case(out_sel)
	3'b001:out_reg<=io_data;
	3'b010:out_reg<=av_bus_data;
	3'b100:out_reg<=zhiku_data;
	default:out_reg<=8'b1;
	endcase
end

assign out_sel = {zhiku_r_cs,av_cs,io_oe};
assign cs_r = av_cs | io_oe | zhiku_r_cs;
/******data bus output port end*********/

/******data bus input port begin*********/
assign in_reg = cs_w?bus_data:in_reg;

assign cs_w = mem_we | io_we;
assign mem_we = zhiku_w_cs;
/******data bus input port end*********/

//doe and dir
assign dir = !cs_r;
assign doe = rst ? ~cs : 1'b1;
assign cs = cs_r | cs_w;

endmodule