xsimtestbench__paoma3.cpp

通过Xilinx Sparten3E Starter Kit验证程序

static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


static HSim__s6* IF0(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMtestbench__paoma3(const char*);
    HSim__s6 *blk = createworkMtestbench__paoma3(label); 
    return blk;
}


static HSim__s6* IF1(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibMdcm__sp__clock__divide__by__2(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibMdcm__sp__clock__divide__by__2(label); 
    return blk;
}


static HSim__s6* IF2(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibMdcm__sp__clock__lost(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibMdcm__sp__clock__lost(label); 
    return blk;
}


static HSim__s6* IF3(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibMdcm__sp__maximum__period__check(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibMdcm__sp__maximum__period__check(label); 
    return blk;
}


static HSim__s6* IF4(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_b_u_f_g(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_b_u_f_g(label); 
    return blk;
}


static HSim__s6* IF5(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_d_c_m___s_p(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_d_c_m___s_p(label); 
    return blk;
}


static HSim__s6* IF6(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_d_c_m___s_p(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_d_c_m___s_p(label); 
    return blk;
}


static HSim__s6* IF7(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_d_c_m___s_p(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_d_c_m___s_p(label); 
    return blk;
}


static HSim__s6* IF8(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_d_c_m___s_p(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_d_c_m___s_p(label); 
    return blk;
}


static HSim__s6* IF9(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_i_b_u_f_g(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_i_b_u_f_g(label); 
    return blk;
}


static HSim__s6* IF10(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_i_b_u_f_g(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_i_b_u_f_g(label); 
    return blk;
}


static HSim__s6* IF11(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_d_c_m___s_p(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_d_c_m___s_p(label); 
    return blk;
}


static HSim__s6* IF12(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_b_u_f_g(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_b_u_f_g(label); 
    return blk;
}


static HSim__s6* IF13(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMpatern2(const char*);
    HSim__s6 *blk = createworkMpatern2(label); 
    return blk;
}


static HSim__s6* IF14(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMpatern1(const char*);
    HSim__s6 *blk = createworkMpatern1(label); 
    return blk;
}


static HSim__s6* IF15(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMlatch(const char*);
    HSim__s6 *blk = createworkMlatch(label); 
    return blk;
}


static HSim__s6* IF16(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkM_m_u_x(const char*);
    HSim__s6 *blk = createworkM_m_u_x(label); 
    return blk;
}


static HSim__s6* IF17(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkM_fre_div10(const char*);
    HSim__s6 *blk = createworkM_fre_div10(label); 
    return blk;
}


static HSim__s6* IF18(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkM_d_c_m__pao2(const char*);
    HSim__s6 *blk = createworkM_d_c_m__pao2(label); 
    return blk;
}


static HSim__s6* IF19(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMpaomadeng(const char*);
    HSim__s6 *blk = createworkMpaomadeng(label); 
    return blk;
}


static HSim__s6* IF20(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMglbl(const char*);
    HSim__s6 *blk = createworkMglbl(label); 
    return blk;
}

class _top : public HSim__s6 {
public:
    _top() : HSim__s6(false, "_top", "_top", 0, 0, HSim::VerilogModule) {}
    HSimConfigDecl * topModuleInstantiate() {
        HSimConfigDecl * cfgvh = 0;
        cfgvh = new HSimConfigDecl("default");
        (*cfgvh).addVlogModule("testbench_paoma3", (HSimInstFactoryPtr)IF0);
        (*cfgvh).addVlogModule("dcm_sp_clock_divide_by_2", (HSimInstFactoryPtr)IF1);
        (*cfgvh).addVlogModule("dcm_sp_clock_lost", (HSimInstFactoryPtr)IF2);
        (*cfgvh).addVlogModule("dcm_sp_maximum_period_check", (HSimInstFactoryPtr)IF3);
        (*cfgvh).addVlogModule("BUFG", (HSimInstFactoryPtr)IF4);
        (*cfgvh).addVlogModule("DCM_SP", (HSimInstFactoryPtr)IF5);
        (*cfgvh).addVlogModule("DCM_SP", (HSimInstFactoryPtr)IF6);
        (*cfgvh).addVlogModule("DCM_SP", (HSimInstFactoryPtr)IF7);
        (*cfgvh).addVlogModule("DCM_SP", (HSimInstFactoryPtr)IF8);
        (*cfgvh).addVlogModule("IBUFG", (HSimInstFactoryPtr)IF9);
        (*cfgvh).addVlogModule("IBUFG", (HSimInstFactoryPtr)IF10);
        (*cfgvh).addVlogModule("DCM_SP", (HSimInstFactoryPtr)IF11);
        (*cfgvh).addVlogModule("BUFG", (HSimInstFactoryPtr)IF12);
        (*cfgvh).addVlogModule("patern2", (HSimInstFactoryPtr)IF13);
        (*cfgvh).addVlogModule("patern1", (HSimInstFactoryPtr)IF14);
        (*cfgvh).addVlogModule("latch", (HSimInstFactoryPtr)IF15);
        (*cfgvh).addVlogModule("MUX", (HSimInstFactoryPtr)IF16);
        (*cfgvh).addVlogModule("FreDiv10", (HSimInstFactoryPtr)IF17);
        (*cfgvh).addVlogModule("DCM_pao2", (HSimInstFactoryPtr)IF18);
        (*cfgvh).addVlogModule("paomadeng", (HSimInstFactoryPtr)IF19);
        (*cfgvh).addVlogModule("glbl", (HSimInstFactoryPtr)IF20);
        HSim__s5 * topvl = 0;
        extern HSim__s6 * createworkMtestbench__paoma3(const char*);
        topvl = (HSim__s5*)createworkMtestbench__paoma3("testbench_paoma3");
        topvl->moduleInstantiate(cfgvh);
        addChild(topvl);
        extern HSim__s6 * createworkMglbl(const char*);
        topvl = (HSim__s5*)createworkMglbl("glbl");
        topvl->moduleInstantiate(cfgvh);
        addChild(topvl);
        return cfgvh;
}
};

main(int argc, char **argv) {
  HSimDesign::initDesign();
  globalKernel->getOptions(argc,argv);
  HSim__s6 * _top_i = 0;
  try {
    HSimConfigDecl *cfg;
 _top_i = new _top();
  cfg =  _top_i->topModuleInstantiate();
    return globalKernel->runTcl(cfg, _top_i, "_top", argc, argv);
  }
  catch (HSimError& msg){
    try {
      globalKernel->error(msg.ErrMsg);
      return 1;
    }
    catch(...) {}
      return 1;
  }
  catch (...){
    globalKernel->fatalError();
    return 1;
  }
}