busis-optimized.trt
来自「vhdl编程实例」· TRT 代码 · 共 383 行 · 第 1/2 页
TRT
383 行
pch1 20.00 11.30 (RC,wr)
pch1 20.00 11.30 (RC,wr)
pch0 n/a n/a (RC,wr)
pch0 n/a n/a (RC,wr)
pch0 20.00 11.30 (RC,wr)
pch0 20.00 11.30 (RC,wr)
d7 -2.60 -2.60 (RC,wr)
d7 -2.60 -2.60 (RC,wr)
d7 10.00 1.50 (RC,wr)
d7 10.00 1.50 (RC,wr)
d6 n/a n/a (RC,wr)
d6 n/a n/a (RC,wr)
d6 10.00 1.50 (RC,wr)
d6 10.00 1.50 (RC,wr)
d5 n/a n/a (RC,wr)
d5 n/a n/a (RC,wr)
d5 10.00 1.50 (RC,wr)
d5 10.00 1.50 (RC,wr)
d4 n/a n/a (RC,wr)
d4 n/a n/a (RC,wr)
d4 10.00 1.50 (RC,wr)
d4 10.00 1.50 (RC,wr)
d3 n/a n/a (RC,wr)
d3 n/a n/a (RC,wr)
d3 20.00 11.50 (RC,wr)
d3 20.00 11.50 (RC,wr)
d2 n/a n/a (RC,wr)
d2 n/a n/a (RC,wr)
d2 20.00 11.50 (RC,wr)
d2 20.00 11.50 (RC,wr)
d1 n/a n/a (RC,wr)
d1 n/a n/a (RC,wr)
d1 20.00 11.50 (RC,wr)
d1 20.00 11.50 (RC,wr)
d0 n/a n/a (RC,wr)
d0 n/a n/a (RC,wr)
d0 20.00 11.50 (RC,wr)
d0 20.00 11.50 (RC,wr)
Output Port Timing:
-------------------
Required Estimated
Port Delay Slack
Name (ns) (ns) From-Group
............................................................
pa7 n/a n/a (RC,wr)
pa7 n/a n/a (RC,wr)
pa7 20.00 11.30 (RC,wr)
pa7 20.00 11.30 (RC,wr)
pa6 n/a n/a (RC,wr)
pa6 n/a n/a (RC,wr)
pa6 20.00 11.30 (RC,wr)
pa6 20.00 11.30 (RC,wr)
pa5 n/a n/a (RC,wr)
pa5 n/a n/a (RC,wr)
pa5 20.00 11.30 (RC,wr)
pa5 20.00 11.30 (RC,wr)
pa4 n/a n/a (RC,wr)
pa4 n/a n/a (RC,wr)
pa4 20.00 11.30 (RC,wr)
pa4 20.00 11.30 (RC,wr)
pa3 n/a n/a (RC,wr)
pa3 n/a n/a (RC,wr)
pa3 20.00 11.30 (RC,wr)
pa3 20.00 11.30 (RC,wr)
pa2 n/a n/a (RC,wr)
pa2 n/a n/a (RC,wr)
pa2 20.00 11.30 (RC,wr)
pa2 20.00 11.30 (RC,wr)
pa1 n/a n/a (RC,wr)
pa1 n/a n/a (RC,wr)
pa1 20.00 11.30 (RC,wr)
pa1 20.00 11.30 (RC,wr)
pa0 n/a n/a (RC,wr)
pa0 n/a n/a (RC,wr)
pa0 20.00 11.30 (RC,wr)
pa0 20.00 11.30 (RC,wr)
pb7 n/a n/a (RC,wr)
pb7 n/a n/a (RC,wr)
pb7 20.00 11.30 (RC,wr)
pb7 20.00 11.30 (RC,wr)
pb6 n/a n/a (RC,wr)
pb6 n/a n/a (RC,wr)
pb6 20.00 11.30 (RC,wr)
pb6 20.00 11.30 (RC,wr)
pb5 n/a n/a (RC,wr)
pb5 n/a n/a (RC,wr)
pb5 20.00 11.30 (RC,wr)
pb5 20.00 11.30 (RC,wr)
pb4 n/a n/a (RC,wr)
pb4 n/a n/a (RC,wr)
pb4 20.00 11.30 (RC,wr)
pb4 20.00 11.30 (RC,wr)
pb3 n/a n/a (RC,wr)
pb3 n/a n/a (RC,wr)
pb3 20.00 11.30 (RC,wr)
pb3 20.00 11.30 (RC,wr)
pb2 n/a n/a (RC,wr)
pb2 n/a n/a (RC,wr)
pb2 20.00 11.30 (RC,wr)
pb2 20.00 11.30 (RC,wr)
pb1 n/a n/a (RC,wr)
pb1 n/a n/a (RC,wr)
pb1 20.00 11.30 (RC,wr)
pb1 20.00 11.30 (RC,wr)
pb0 n/a n/a (RC,wr)
pb0 n/a n/a (RC,wr)
pb0 20.00 11.30 (RC,wr)
pb0 20.00 11.30 (RC,wr)
pcl3 n/a n/a (RC,wr)
pcl3 n/a n/a (RC,wr)
pcl3 20.00 11.30 (RC,wr)
pcl3 20.00 11.30 (RC,wr)
pcl2 n/a n/a (RC,wr)
pcl2 n/a n/a (RC,wr)
pcl2 20.00 11.30 (RC,wr)
pcl2 20.00 11.30 (RC,wr)
pcl1 n/a n/a (RC,wr)
pcl1 n/a n/a (RC,wr)
pcl1 20.00 11.30 (RC,wr)
pcl1 20.00 11.30 (RC,wr)
pcl0 n/a n/a (RC,wr)
pcl0 n/a n/a (RC,wr)
pcl0 20.00 11.30 (RC,wr)
pcl0 20.00 11.30 (RC,wr)
pch3 n/a n/a (RC,wr)
pch3 n/a n/a (RC,wr)
pch3 20.00 11.30 (RC,wr)
pch3 20.00 11.30 (RC,wr)
pch2 n/a n/a (RC,wr)
pch2 n/a n/a (RC,wr)
pch2 20.00 11.30 (RC,wr)
pch2 20.00 11.30 (RC,wr)
pch1 n/a n/a (RC,wr)
pch1 n/a n/a (RC,wr)
pch1 20.00 11.30 (RC,wr)
pch1 20.00 11.30 (RC,wr)
pch0 n/a n/a (RC,wr)
pch0 n/a n/a (RC,wr)
pch0 20.00 11.30 (RC,wr)
pch0 20.00 11.30 (RC,wr)
d7 -2.60 -2.60 (RC,wr)
d7 -2.60 -2.60 (RC,wr)
d7 10.00 1.50 (RC,wr)
d7 10.00 1.50 (RC,wr)
d6 n/a n/a (RC,wr)
d6 n/a n/a (RC,wr)
d6 10.00 1.50 (RC,wr)
d6 10.00 1.50 (RC,wr)
d5 n/a n/a (RC,wr)
d5 n/a n/a (RC,wr)
d5 10.00 1.50 (RC,wr)
d5 10.00 1.50 (RC,wr)
d4 n/a n/a (RC,wr)
d4 n/a n/a (RC,wr)
d4 10.00 1.50 (RC,wr)
d4 10.00 1.50 (RC,wr)
d3 n/a n/a (RC,wr)
d3 n/a n/a (RC,wr)
d3 20.00 11.50 (RC,wr)
d3 20.00 11.50 (RC,wr)
d2 n/a n/a (RC,wr)
d2 n/a n/a (RC,wr)
d2 20.00 11.50 (RC,wr)
d2 20.00 11.50 (RC,wr)
d1 n/a n/a (RC,wr)
d1 n/a n/a (RC,wr)
d1 20.00 11.50 (RC,wr)
d1 20.00 11.50 (RC,wr)
d0 n/a n/a (RC,wr)
d0 n/a n/a (RC,wr)
d0 20.00 11.50 (RC,wr)
d0 20.00 11.50 (RC,wr)
Critical Path Timing:
---------------------
Arrival Required
Cell Time Time Fanout
Type (ns) (ns) Count Pin-Name
.........................................................
DFFE 26.30 20.00 34 /busis-Optimized/pc_l
DFFE 23.50 17.20 1 /busis-Optimized/pc_l
LUT 23.50 17.20 1 /busis-Optimized/C116
LUT 16.90 10.60 4 /busis-Optimized/C116
LUT 16.90 10.60 4 /busis-Optimized/C116
LUT 10.30 4.00 17 /busis-Optimized/C116
LUT 10.30 4.00 17 /busis-Optimized/C116
LUT 3.70 -2.60 4 /busis-Optimized/C116
DFFE 3.70 -2.60 4 /busis-Optimized/conr
DFFE 0.00 -6.30 34 /busis-Optimized/conr
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