48_fir_tb_1.v

本次设计的数字基带成形滤波器参照IS-95标准进行设计

`timescale 1 ns / 1 ns

module filter_tb_48_1;

  // Parameters
  parameter clk_high   = 5;
  parameter clk_low    = 5;
  parameter clk_period = 10;
  parameter clk_hold   = 2;

  // Nets
  reg clk;
  reg clk_enable;
  reg reset;
  reg  signed [19:0] filter_in;
  wire signed  [19:0] filter_out;

  integer n;  //loop variable


  reg signed [15:0] filter_in_force [0:100];
  reg signed [15:0] filter_out_expected [0:100];

  // Function definitions
  function real abs_real;
  input real arg;
  begin
    abs_real = arg > 0 ? arg : -arg;
  end
  endfunction //function abs_real

  // Component Instances
  base_48_fir u_filter_48
    (
    .filter_out(filter_out),
    .filter_in(filter_in),
    .clk(clk),
    .reset(reset),
    .clk_enable(clk_enable)
    );
initial
      begin
          filter_in_force [0] <= 0;
          filter_in_force [1] <= 1;
          filter_in_force [2] <= 1;
          filter_in_force [3] <=1;
          filter_in_force [4] <=0;
          filter_in_force [5] <=0;
          filter_in_force [6] <=1;
          filter_in_force [7] <=1;
          filter_in_force [8] <=0;
          filter_in_force [9] <=1;
          filter_in_force [10] <=0;
          filter_in_force [11] <=1;
          filter_in_force [12] <=1;
          filter_in_force [13] <=0;
          filter_in_force [14] <=1;
          filter_in_force [15] <=1;
          filter_in_force [16] <=1;
          filter_in_force [17] <=1;
          filter_in_force [18] <=0;
          filter_in_force [19] <=0;
          filter_in_force [20] <=0;
          filter_in_force [21] <=1;
          filter_in_force [22] <=1;
          filter_in_force [23] <=1;
          filter_in_force [24] <=0;
          filter_in_force [25] <=1;
          filter_in_force [26] <=1;
          filter_in_force [27] <=1;
          filter_in_force [28] <=1;
          filter_in_force [29] <=0;
          filter_in_force [30] <=0;
          filter_in_force [31] <=1;
          filter_in_force [32] <=1;
          filter_in_force [33] <=1;
          filter_in_force [34] <=0;
          filter_in_force [35] <=1;
          filter_in_force [36] <=1;
          filter_in_force [37] <=1;
          filter_in_force [38] <=1;
          filter_in_force [39] <=0;
          filter_in_force [30] <=0;
          filter_in_force [41] <=1;
          filter_in_force [42] <=1;
          filter_in_force [43] <=0;
          filter_in_force [44] <=1;
          filter_in_force [45] <=1;
          filter_in_force [46] <=1;
          filter_in_force [47] <=1;
          filter_in_force [48] <=0;
          filter_in_force [49] <=0;
          filter_in_force [50] <=0;
          filter_in_force [51] <=1;
          filter_in_force [52] <=1;
          filter_in_force [53] <=0;
          filter_in_force [54] <=1;
          filter_in_force [55] <=1;
          filter_in_force [56] <=1;
          filter_in_force [57] <=1;
          filter_in_force [58] <=0;
          filter_in_force [59] <=1;
          filter_in_force [60] <=0;
          filter_in_force [61] <=1;
          filter_in_force [62] <=1;
          filter_in_force [63] <=1;
          filter_in_force [64] <=0;
          filter_in_force [65] <=1;
          filter_in_force [66] <=1;
          filter_in_force [67] <=0;
          filter_in_force [68] <=1;
          filter_in_force [69] <=0;
          filter_in_force [70] <=0;
          filter_in_force [71] <=1;
          filter_in_force [72] <=1;
          filter_in_force [73] <=1;
          filter_in_force [74] <=0;
          filter_in_force [75] <=1;
          filter_in_force [76] <=0;
          filter_in_force [77] <=1;
          filter_in_force [78] <=1;
          filter_in_force [79] <=0;
          filter_in_force [80] <=0;
          filter_in_force [81] <=1;
          filter_in_force [82] <=1;
          filter_in_force [83] <=0;
          filter_in_force [84] <=1;
          filter_in_force [85] <=1;
          filter_in_force [86] <=0;
          filter_in_force [87] <=1;
          filter_in_force [88] <=0;
          filter_in_force [89] <=1;
          filter_in_force [90] <=0;
          filter_in_force [91] <=1;
          filter_in_force [92] <=1;
          filter_in_force [93] <=0;
          filter_in_force [94] <=1;
          filter_in_force [95] <=1;
          filter_in_force [96] <=0;
          filter_in_force [97] <=1;
          filter_in_force [98] <=0;
          filter_in_force [99] <=0;
          filter_in_force [100] <=1;
      end
    // Block Statements
  always  // clk generation
    begin : clk_gen
    clk <= 1'b1;
    # clk_high;
    clk <= 1'b0;
    # clk_low;
    end  //clk_gen;

  initial  // reset block
    begin : reset_gen
    clk_enable <= 1'b1;
    reset <= 1'b1;
    # (clk_period*2 + clk_hold);
    reset <= 1'b0;
  end  //reset_gen;

  initial  //The main block 
    begin
    # clk_period;
    filter_in <= filter_in_force[0];
    # (clk_period*2 + clk_hold);
    filter_in <= filter_in_force[1];
    # clk_period;
    for (n = 0; n<= 100; n = n + 1)
      begin
      if (abs_real($bitstoreal(filter_out) - $bitstoreal(filter_out_expected[n])) >= 1.0e-9)
        $display("ERROR in filter test at time %t : Expected '%f' Actual '%f'", $time, $bitstoreal(filter_out_expected[n]), $bitstoreal(filter_out));
      if (n + 2 <= 100)
        filter_in <= filter_in_force[n + 2];
      # (clk_period);
      end
    $display( "**** Test Complete. ****" );
    $stop;

  end //filter_in_gen;

endmodule