de2_lcm_test.map.rpt

NIOS下

+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: I2S_LCM_Config:u4|I2S_Controller:u0 ;
+----------------+----------+------------------------------------------------------+
; Parameter Name ; Value    ; Type                                                 ;
+----------------+----------+------------------------------------------------------+
; CLK_Freq       ; 50000000 ; Integer                                              ;
; I2S_Freq       ; 20000    ; Integer                                              ;
+----------------+----------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Jul 30 10:36:35 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_LCM_Test -c DE2_LCM_Test
Info: Found 1 design units, including 1 entities, in source file I2S_LCM_Config.v
    Info: Found entity 1: I2S_LCM_Config
Warning (10236): Verilog HDL net warning at DE2_LCM_Test.v(75): created undeclared net "TD_RESET"
Warning (10238): Verilog Module Declaration warning at DE2_LCM_Test.v(24): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "DE2_LCM_Test"
Info: Found 1 design units, including 1 entities, in source file DE2_LCM_Test.v
    Info: Found entity 1: DE2_LCM_Test
Info: Found 1 design units, including 1 entities, in source file I2S_Controller.v
    Info: Found entity 1: I2S_Controller
Info: Elaborating entity "DE2_LCM_Test" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at DE2_LCM_Test.v(109): object "H_SYNC_ACT" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_LCM_Test.v(114): object "V_SYNC_BACK" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_LCM_Test.v(115): object "V_SYNC_ACT" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_LCM_Test.v(116): object "V_SYNC_FRONT" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_LCM_Test.v(75): object "TD_RESET" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at DE2_LCM_Test.v(160): truncated value with size 32 to match size of target (11)
Warning (10230): Verilog HDL assignment warning at DE2_LCM_Test.v(186): truncated value with size 32 to match size of target (11)
Warning (10230): Verilog HDL assignment warning at DE2_LCM_Test.v(201): truncated value with size 32 to match size of target (18)
Warning (10034): Output port "I2C_SCLK" at DE2_LCM_Test.v(43) has no driver
Warning: Using design file LCM_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: LCM_PLL
Info: Elaborating entity "LCM_PLL" for hierarchy "LCM_PLL:u0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "LCM_PLL:u0|altpll:altpll_component"
Info: Elaborated megafunction instantiation "LCM_PLL:u0|altpll:altpll_component"
Info: Elaborating entity "I2S_LCM_Config" for hierarchy "I2S_LCM_Config:u4"
Warning (10230): Verilog HDL assignment warning at I2S_LCM_Config.v(71): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "I2S_Controller" for hierarchy "I2S_LCM_Config:u4|I2S_Controller:u0"
Warning (10230): Verilog HDL assignment warning at I2S_Controller.v(90): truncated value with size 32 to match size of target (16)
Warning: Reduced register "I2S_LCM_Config:u4|mI2S_DATA[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2S_LCM_Config:u4|mI2S_DATA[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2S_LCM_Config:u4|mI2S_DATA[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2S_LCM_Config:u4|mI2S_DATA[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2S_LCM_Config:u4|mI2S_DATA[6]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "I2S_LCM_Config:u4|mI2S_DATA[2]" merged to single register "I2S_LCM_Config:u4|mI2S_DATA[3]"
Info: State machine "|DE2_LCM_Test|I2S_LCM_Config:u4|mSetup_ST" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|DE2_LCM_Test|I2S_LCM_Config:u4|mSetup_ST"
Info: Encoding result for state machine "|DE2_LCM_Test|I2S_LCM_Config:u4|mSetup_ST"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "I2S_LCM_Config:u4|mSetup_ST.0000"
        Info: Encoded state bit "I2S_LCM_Config:u4|mSetup_ST.0010"
        Info: Encoded state bit "I2S_LCM_Config:u4|mSetup_ST.0001"
    Info: State "|DE2_LCM_Test|I2S_LCM_Config:u4|mSetup_ST.0000" uses code string "000"
    Info: State "|DE2_LCM_Test|I2S_LCM_Config:u4|mSetup_ST.0001" uses code string "101"
    Info: State "|DE2_LCM_Test|I2S_LCM_Config:u4|mSetup_ST.0010" uses code string "110"
Warning: The bidir "I2C_SDAT" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[9]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[10]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[11]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[12]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[13]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[14]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[15]" has no source; inserted an always disabled tri-state buffer.
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[18]~17 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[19]~16 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[20]~15 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[21]~14 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[22]~13 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[23]~12 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[24]~11 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[25]~10 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[26]~9 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[28]~7 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[29]~6 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[30]~5 that it feeds
Warning: Replaced VCC or GND feeding tri-state bus GPIO_0[31]~4 with an always-enabled tri-state buffer
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[33]~2 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_0[35]~0 that it feeds
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~176 to tri-state bus GPIO_0[18]~17
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~177 to tri-state bus GPIO_0[19]~16
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~178 to tri-state bus GPIO_0[20]~15
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~179 to tri-state bus GPIO_0[21]~14
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~180 to tri-state bus GPIO_0[22]~13
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~181 to tri-state bus GPIO_0[23]~12
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~182 to tri-state bus GPIO_0[24]~11
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~183 to tri-state bus GPIO_0[25]~10
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~184 to tri-state bus GPIO_0[26]~9
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~186 to tri-state bus GPIO_0[28]~7
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~187 to tri-state bus GPIO_0[29]~6
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~188 to tri-state bus GPIO_0[30]~5
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~189 to tri-state bus GPIO_0[31]~4
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~191 to tri-state bus GPIO_0[33]~2
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~192 to tri-state bus GPIO_0[34]~1
Warning: Removed fan-in from always-disabled I/O buffer GPIO_0~193 to tri-state bus GPIO_0[35]~0
Warning: Converting TRI node "I2S_LCM_Config:u4|I2S_Controller:u0|I2S_DATA~1" that feeds logic to an OR gate
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "GPIO_0[18]~143"
    Warning: Node "GPIO_0[19]~144"
    Warning: Node "GPIO_0[20]~145"
    Warning: Node "GPIO_0[21]~146"
    Warning: Node "GPIO_0[22]~147"
    Warning: Node "GPIO_0[23]~148"
    Warning: Node "GPIO_0[24]~149"
    Warning: Node "GPIO_0[25]~150"
    Warning: Node "GPIO_0[26]~151"
    Warning: Node "GPIO_0[28]~152"
    Warning: Node "GPIO_0[29]~153"
    Warning: Node "GPIO_0[30]~154"
    Warning: Node "GPIO_0[31]~155"
    Warning: Node "GPIO_0[33]~156"
    Warning: Node "GPIO_0[35]~157"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "SRAM_UB_N" stuck at GND
    Warning: Pin "SRAM_LB_N" stuck at GND
    Warning: Pin "SRAM_WE_N" stuck at VCC
    Warning: Pin "SRAM_CE_N" stuck at GND
    Warning: Pin "SRAM_OE_N" stuck at GND
    Warning: Pin "I2C_SCLK" stuck at GND
Warning: Design contains 22 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "CLOCK_27"
    Warning: No output dependent on input pin "KEY[1]"
    Warning: No output dependent on input pin "KEY[2]"
    Warning: No output dependent on input pin "KEY[3]"
    Warning: No output dependent on input pin "SW[0]"
    Warning: No output dependent on input pin "SW[1]"
    Warning: No output dependent on input pin "SW[2]"
    Warning: No output dependent on input pin "SW[3]"
    Warning: No output dependent on input pin "SW[4]"
    Warning: No output dependent on input pin "SW[5]"
    Warning: No output dependent on input pin "SW[6]"
    Warning: No output dependent on input pin "SW[7]"
    Warning: No output dependent on input pin "SW[8]"
    Warning: No output dependent on input pin "SW[9]"
    Warning: No output dependent on input pin "SW[10]"
    Warning: No output dependent on input pin "SW[11]"
    Warning: No output dependent on input pin "SW[12]"
    Warning: No output dependent on input pin "SW[13]"
    Warning: No output dependent on input pin "SW[14]"
    Warning: No output dependent on input pin "SW[15]"
    Warning: No output dependent on input pin "SW[16]"
    Warning: No output dependent on input pin "SW[17]"
Info: Implemented 284 device resources after synthesis - the final resource count might be different
    Info: Implemented 24 input pins
    Info: Implemented 24 output pins
    Info: Implemented 53 bidirectional pins
    Info: Implemented 182 logic cells
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 114 warnings
    Info: Processing ended: Mon Jul 30 10:36:38 2007
    Info: Elapsed time: 00:00:05