de2_lcm_test.map.qmsg

NIOS下

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 30 10:36:35 2007 " "Info: Processing started: Mon Jul 30 10:36:35 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE2_LCM_Test -c DE2_LCM_Test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_LCM_Test -c DE2_LCM_Test" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2S_LCM_Config.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2S_LCM_Config.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2S_LCM_Config " "Info: Found entity 1: I2S_LCM_Config" {  } { { "I2S_LCM_Config.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_LCM_Config.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "TD_RESET DE2_LCM_Test.v(75) " "Warning (10236): Verilog HDL net warning at DE2_LCM_Test.v(75): created undeclared net \"TD_RESET\"" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 75 0 0 } }  } 0 10236 "Verilog HDL net warning at %2!s!: created undeclared net \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "DE2_LCM_Test DE2_LCM_Test.v(24) " "Warning (10238): Verilog Module Declaration warning at DE2_LCM_Test.v(24): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"DE2_LCM_Test\"" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 24 0 0 } }  } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DE2_LCM_Test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DE2_LCM_Test.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_LCM_Test " "Info: Found entity 1: DE2_LCM_Test" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2S_Controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2S_Controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2S_Controller " "Info: Found entity 1: I2S_Controller" {  } { { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DE2_LCM_Test " "Info: Elaborating entity \"DE2_LCM_Test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "H_SYNC_ACT DE2_LCM_Test.v(109) " "Warning (10036): Verilog HDL or VHDL warning at DE2_LCM_Test.v(109): object \"H_SYNC_ACT\" assigned a value but never read" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 109 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "V_SYNC_BACK DE2_LCM_Test.v(114) " "Warning (10036): Verilog HDL or VHDL warning at DE2_LCM_Test.v(114): object \"V_SYNC_BACK\" assigned a value but never read" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 114 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "V_SYNC_ACT DE2_LCM_Test.v(115) " "Warning (10036): Verilog HDL or VHDL warning at DE2_LCM_Test.v(115): object \"V_SYNC_ACT\" assigned a value but never read" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 115 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "V_SYNC_FRONT DE2_LCM_Test.v(116) " "Warning (10036): Verilog HDL or VHDL warning at DE2_LCM_Test.v(116): object \"V_SYNC_FRONT\" assigned a value but never read" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 116 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "TD_RESET DE2_LCM_Test.v(75) " "Warning (10036): Verilog HDL or VHDL warning at DE2_LCM_Test.v(75): object \"TD_RESET\" assigned a value but never read" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 75 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 DE2_LCM_Test.v(160) " "Warning (10230): Verilog HDL assignment warning at DE2_LCM_Test.v(160): truncated value with size 32 to match size of target (11)" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 160 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 DE2_LCM_Test.v(186) " "Warning (10230): Verilog HDL assignment warning at DE2_LCM_Test.v(186): truncated value with size 32 to match size of target (11)" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 186 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 DE2_LCM_Test.v(201) " "Warning (10230): Verilog HDL assignment warning at DE2_LCM_Test.v(201): truncated value with size 32 to match size of target (18)" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "I2C_SCLK DE2_LCM_Test.v(43) " "Warning (10034): Output port \"I2C_SCLK\" at DE2_LCM_Test.v(43) has no driver" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 43 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "LCM_PLL.v 1 1 " "Warning: Using design file LCM_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 LCM_PLL " "Info: Found entity 1: LCM_PLL" {  } { { "LCM_PLL.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/LCM_PLL.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LCM_PLL LCM_PLL:u0 " "Info: Elaborating entity \"LCM_PLL\" for hierarchy \"LCM_PLL:u0\"" {  } { { "DE2_LCM_Test.v" "u0" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 119 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll LCM_PLL:u0\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"LCM_PLL:u0\|altpll:altpll_component\"" {  } { { "LCM_PLL.v" "altpll_component" { Text "E:/EDA_DESIGN/DE2_LCM_Test/LCM_PLL.v" 79 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "LCM_PLL:u0\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"LCM_PLL:u0\|altpll:altpll_component\"" {  } { { "LCM_PLL.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/LCM_PLL.v" 79 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2S_LCM_Config I2S_LCM_Config:u4 " "Info: Elaborating entity \"I2S_LCM_Config\" for hierarchy \"I2S_LCM_Config:u4\"" {  } { { "DE2_LCM_Test.v" "u4" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 215 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}