de2_lcm_test.tan.qmsg

NIOS下

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 register oVGA_V_SYNC register oVGA_V_SYNC 391 ps " "Info: Minimum slack time is 391 ps for clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" between source register \"oVGA_V_SYNC\" and destination register \"oVGA_V_SYNC\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Shortest register register " "Info: + Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns oVGA_V_SYNC 1 REG LCFF_X30_Y8_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y8_N9; Fanout = 2; REG Node = 'oVGA_V_SYNC'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { oVGA_V_SYNC } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns oVGA_V_SYNC~139 2 COMB LCCOMB_X30_Y8_N8 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X30_Y8_N8; Fanout = 1; COMB Node = 'oVGA_V_SYNC~139'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { oVGA_V_SYNC oVGA_V_SYNC~139 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns oVGA_V_SYNC 3 REG LCFF_X30_Y8_N9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X30_Y8_N9; Fanout = 2; REG Node = 'oVGA_V_SYNC'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { oVGA_V_SYNC~139 oVGA_V_SYNC } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { oVGA_V_SYNC oVGA_V_SYNC~139 oVGA_V_SYNC } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { oVGA_V_SYNC oVGA_V_SYNC~139 oVGA_V_SYNC } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.016 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.016 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.358 ns " "Info: + Latch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination LCM_PLL:u0\|altpll:altpll_component\|_clk0 54.285 ns -2.358 ns  50 " "Info: Clock period of Destination clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" is 54.285 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source LCM_PLL:u0\|altpll:altpll_component\|_clk0 54.285 ns -2.358 ns  50 " "Info: Clock period of Source clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" is 54.285 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 destination 2.651 ns + Longest register " "Info: + Longest clock path from clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" to destination register is 2.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCM_PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 51 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 51; COMB Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.537 ns) 2.651 ns oVGA_V_SYNC 3 REG LCFF_X30_Y8_N9 2 " "Info: 3: + IC(1.023 ns) + CELL(0.537 ns) = 2.651 ns; Loc. = LCFF_X30_Y8_N9; Fanout = 2; REG Node = 'oVGA_V_SYNC'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.560 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.114 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.114 ns ( 79.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } { 0.000ns 1.091ns 1.023ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 source 2.651 ns - Shortest register " "Info: - Shortest clock path from clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" to source register is 2.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCM_PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 51 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 51; COMB Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.537 ns) 2.651 ns oVGA_V_SYNC 3 REG LCFF_X30_Y8_N9 2 " "Info: 3: + IC(1.023 ns) + CELL(0.537 ns) = 2.651 ns; Loc. = LCFF_X30_Y8_N9; Fanout = 2; REG Node = 'oVGA_V_SYNC'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.560 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.114 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.114 ns ( 79.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } { 0.000ns 1.091ns 1.023ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } { 0.000ns 1.091ns 1.023ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } { 0.000ns 1.091ns 1.023ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosur