📄 de2_lcm_test.tan.qmsg
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{ "Info" "ITDB_FULL_SLACK_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 register V_Cont\[0\] register iSRAM_ADDR\[17\] 45.095 ns " "Info: Slack time is 45.095 ns for clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" between source register \"V_Cont\[0\]\" and destination register \"iSRAM_ADDR\[17\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "108.81 MHz 9.19 ns " "Info: Fmax is 108.81 MHz (period= 9.19 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "54.089 ns + Largest register register " "Info: + Largest register to register requirement is 54.089 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "54.285 ns + " "Info: + Setup relationship between source and destination is 54.285 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 51.927 ns " "Info: + Latch edge is 51.927 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination LCM_PLL:u0\|altpll:altpll_component\|_clk0 54.285 ns -2.358 ns 50 " "Info: Clock period of Destination clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" is 54.285 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source LCM_PLL:u0\|altpll:altpll_component\|_clk0 54.285 ns -2.358 ns 50 " "Info: Clock period of Source clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" is 54.285 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.018 ns + Largest " "Info: + Largest clock skew is 0.018 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 destination 2.669 ns + Shortest register " "Info: + Shortest clock path from clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" to destination register is 2.669 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCM_PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 51 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 51; COMB Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.537 ns) 2.669 ns iSRAM_ADDR\[17\] 3 REG LCFF_X18_Y1_N17 1 " "Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.669 ns; Loc. = LCFF_X18_Y1_N17; Fanout = 1; REG Node = 'iSRAM_ADDR\[17\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.578 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl iSRAM_ADDR[17] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.12 % ) " "Info: Total cell delay = 0.537 ns ( 20.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.132 ns ( 79.88 % ) " "Info: Total interconnect delay = 2.132 ns ( 79.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.669 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl iSRAM_ADDR[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.669 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl iSRAM_ADDR[17] } { 0.000ns 1.091ns 1.041ns } { 0.000ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 source 2.651 ns - Longest register " "Info: - Longest clock path from clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" to source register is 2.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCM_PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 51 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 51; COMB Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.537 ns) 2.651 ns V_Cont\[0\] 3 REG LCFF_X29_Y8_N7 7 " "Info: 3: + IC(1.023 ns) + CELL(0.537 ns) = 2.651 ns; Loc. = LCFF_X29_Y8_N7; Fanout = 7; REG Node = 'V_Cont\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.560 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl V_Cont[0] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.114 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.114 ns ( 79.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl V_Cont[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl V_Cont[0] } { 0.000ns 1.091ns 1.023ns } { 0.000ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.669 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl iSRAM_ADDR[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.669 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl iSRAM_ADDR[17] } { 0.000ns 1.091ns 1.041ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl V_Cont[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl V_Cont[0] } { 0.000ns 1.091ns 1.023ns } { 0.000ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 206 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.669 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl iSRAM_ADDR[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.669 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl iSRAM_ADDR[17] } { 0.000ns 1.091ns 1.041ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl V_Cont[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl V_Cont[0] } { 0.000ns 1.091ns 1.023ns } { 0.000ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.994 ns - Longest register register " "Info: - Longest register to register delay is 8.994 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns V_Cont\[0\] 1 REG LCFF_X29_Y8_N7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y8_N7; Fanout = 7; REG Node = 'V_Cont\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { V_Cont[0] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.808 ns) + CELL(0.414 ns) 1.222 ns Add2~171 2 COMB LCCOMB_X29_Y7_N0 2 " "Info: 2: + IC(0.808 ns) + CELL(0.414 ns) = 1.222 ns; Loc. = LCCOMB_X29_Y7_N0; Fanout = 2; COMB Node = 'Add2~171'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.222 ns" { V_Cont[0] Add2~171 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.293 ns Add2~173 3 COMB LCCOMB_X29_Y7_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.293 ns; Loc. = LCCOMB_X29_Y7_N2; Fanout = 2; COMB Node = 'Add2~173'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add2~171 Add2~173 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.703 ns Add2~174 4 COMB LCCOMB_X29_Y7_N4 3 " "Info: 4: + IC(0.000 ns) + CELL(0.410 ns) = 1.703 ns; Loc. = LCCOMB_X29_Y7_N4; Fanout = 3; COMB Node = 'Add2~174'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add2~173 Add2~174 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.414 ns) 2.582 ns Add3~191 5 COMB LCCOMB_X28_Y7_N4 1 " "Info: 5: + IC(0.465 ns) + CELL(0.414 ns) = 2.582 ns; Loc. = LCCOMB_X28_Y7_N4; Fanout = 1; COMB Node = 'Add3~191'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.879 ns" { Add2~174 Add3~191 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.653 ns Add3~193 6 COMB LCCOMB_X28_Y7_N6 1 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.653 ns; Loc. = LCCOMB_X28_Y7_N6; Fanout = 1; COMB Node = 'Add3~193'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add3~191 Add3~193 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.724 ns Add3~195 7 COMB LCCOMB_X28_Y7_N8 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.724 ns; Loc. = LCCOMB_X28_Y7_N8; Fanout = 2; COMB Node = 'Add3~195'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add3~193 Add3~195 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.795 ns Add3~197 8 COMB LCCOMB_X28_Y7_N10 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 2.795 ns; Loc. = LCCOMB_X28_Y7_N10; Fanout = 2; COMB Node = 'Add3~197'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add3~195 Add3~197 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.866 ns Add3~199 9 COMB LCCOMB_X28_Y7_N12 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 2.866 ns; Loc. = LCCOMB_X28_Y7_N12; Fanout = 2; COMB Node = 'Add3~199'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add3~197 Add3~199 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 3.025 ns Add3~201 10 COMB LCCOMB_X28_Y7_N14 2 " "Info: 10: + IC(0.000 ns) + CELL(0.159 ns) = 3.025 ns; Loc. = LCCOMB_X28_Y7_N14; Fanout = 2; COMB Node = 'Add3~201'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add3~199 Add3~201 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 3.435 ns Add3~202 11 COMB LCCOMB_X28_Y7_N16 2 " "Info: 11: + IC(0.000 ns) + CELL(0.410 ns) = 3.435 ns; Loc. = LCCOMB_X28_Y7_N16; Fanout = 2; COMB Node = 'Add3~202'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add3~201 Add3~202 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.414 ns) 4.293 ns Add4~209 12 COMB LCCOMB_X27_Y7_N22 2 " "Info: 12: + IC(0.444 ns) + CELL(0.414 ns) = 4.293 ns; Loc. = LCCOMB_X27_Y7_N22; Fanout = 2; COMB Node = 'Add4~209'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.858 ns" { Add3~202 Add4~209 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 4.703 ns Add4~210 13 COMB LCCOMB_X27_Y7_N24 2 " "Info: 13: + IC(0.000 ns) + CELL(0.410 ns) = 4.703 ns; Loc. = LCCOMB_X27_Y7_N24; Fanout = 2; COMB Node = 'Add4~210'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add4~209 Add4~210 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.491 ns) + CELL(0.414 ns) 6.608 ns Add5~202 14 COMB LCCOMB_X20_Y2_N22 2 " "Info: 14: + IC(1.491 ns) + CELL(0.414 ns) = 6.608 ns; Loc. = LCCOMB_X20_Y2_N22; Fanout = 2; COMB Node = 'Add5~202'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.905 ns" { Add4~210 Add5~202 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 6.679 ns Add5~204 15 COMB LCCOMB_X20_Y2_N24 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 6.679 ns; Loc. = LCCOMB_X20_Y2_N24; Fanout = 2; COMB Node = 'Add5~204'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add5~202 Add5~204 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 7.089 ns Add5~205 16 COMB LCCOMB_X20_Y2_N26 2 " "Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 7.089 ns; Loc. = LCCOMB_X20_Y2_N26; Fanout = 2; COMB Node = 'Add5~205'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add5~204 Add5~205 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.504 ns) 8.500 ns iSRAM_ADDR\[16\]~102 17 COMB LCCOMB_X18_Y1_N14 1 " "Info: 17: + IC(0.907 ns) + CELL(0.504 ns) = 8.500 ns; Loc. = LCCOMB_X18_Y1_N14; Fanout = 1; COMB Node = 'iSRAM_ADDR\[16\]~102'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.411 ns" { Add5~205 iSRAM_ADDR[16]~102 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 8.910 ns iSRAM_ADDR\[17\]~86 18 COMB LCCOMB_X18_Y1_N16 1 " "Info: 18: + IC(0.000 ns) + CELL(0.410 ns) = 8.910 ns; Loc. = LCCOMB_X18_Y1_N16; Fanout = 1; COMB Node = 'iSRAM_ADDR\[17\]~86'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { iSRAM_ADDR[16]~102 iSRAM_ADDR[17]~86 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 8.994 ns iSRAM_ADDR\[17\] 19 REG LCFF_X18_Y1_N17 1 " "Info: 19: + IC(0.000 ns) + CELL(0.084 ns) = 8.994 ns; Loc. = LCFF_X18_Y1_N17; Fanout = 1; REG Node = 'iSRAM_ADDR\[17\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { iSRAM_ADDR[17]~86 iSRAM_ADDR[17] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.879 ns ( 54.25 % ) " "Info: Total cell delay = 4.879 ns ( 54.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.115 ns ( 45.75 % ) " "Info: Total interconnect delay = 4.115 ns ( 45.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.994 ns" { V_Cont[0] Add2~171 Add2~173 Add2~174 Add3~191 Add3~193 Add3~195 Add3~197 Add3~199 Add3~201 Add3~202 Add4~209 Add4~210 Add5~202 Add5~204 Add5~205 iSRAM_ADDR[16]~102 iSRAM_ADDR[17]~86 iSRAM_ADDR[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.994 ns" { V_Cont[0] Add2~171 Add2~173 Add2~174 Add3~191 Add3~193 Add3~195 Add3~197 Add3~199 Add3~201 Add3~202 Add4~209 Add4~210 Add5~202 Add5~204 Add5~205 iSRAM_ADDR[16]~102 iSRAM_ADDR[17]~86 iSRAM_ADDR[17] } { 0.000ns 0.808ns 0.000ns 0.000ns 0.465ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.444ns 0.000ns 1.491ns 0.000ns 0.000ns 0.907ns 0.000ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.410ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.410ns 0.414ns 0.410ns 0.414ns 0.071ns 0.410ns 0.504ns 0.410ns 0.084ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.669 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl iSRAM_ADDR[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.669 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl iSRAM_ADDR[17] } { 0.000ns 1.091ns 1.041ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl V_Cont[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.651 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl V_Cont[0] } { 0.000ns 1.091ns 1.023ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.994 ns" { V_Cont[0] Add2~171 Add2~173 Add2~174 Add3~191 Add3~193 Add3~195 Add3~197 Add3~199 Add3~201 Add3~202 Add4~209 Add4~210 Add5~202 Add5~204 Add5~205 iSRAM_ADDR[16]~102 iSRAM_ADDR[17]~86 iSRAM_ADDR[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.994 ns" { V_Cont[0] Add2~171 Add2~173 Add2~174 Add3~191 Add3~193 Add3~195 Add3~197 Add3~199 Add3~201 Add3~202 Add4~209 Add4~210 Add5~202 Add5~204 Add5~205 iSRAM_ADDR[16]~102 iSRAM_ADDR[17]~86 iSRAM_ADDR[17] } { 0.000ns 0.808ns 0.000ns 0.000ns 0.465ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.444ns 0.000ns 1.491ns 0.000ns 0.000ns 0.907ns 0.000ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.410ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.410ns 0.414ns 0.410ns 0.414ns 0.071ns 0.410ns 0.504ns 0.410ns 0.084ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLOCK_50 register I2S_LCM_Config:u4\|mI2S_DATA\[12\] register I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA 8.061 ns " "Info: Slack time is 8.061 ns for clock \"CLOCK_50\" between source register \"I2S_LCM_Config:u4\|mI2S_DATA\[12\]\" and destination register \"I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "257.86 MHz 3.878 ns " "Info: Fmax is 257.86 MHz (period= 3.878 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.786 ns + Largest register register " "Info: + Largest register to register requirement is 9.786 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_50 20.000 ns 10.000 ns inverted 50 " "Info: Clock period of Destination clock \"CLOCK_50\" is 20.000 ns with inverted offset of 10.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLOCK_50 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"CLOCK_50\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 5.843 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 5.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 17 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.787 ns) 2.928 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK 3 REG LCFF_X30_Y8_N25 3 " "Info: 3: + IC(1.024 ns) + CELL(0.787 ns) = 2.928 ns; Loc. = LCFF_X30_Y8_N25; Fanout = 3; REG Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.811 ns" { CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.378 ns) + CELL(0.000 ns) 4.306 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK~clkctrl 4 COMB CLKCTRL_G13 30 " "Info: 4: + IC(1.378 ns) + CELL(0.000 ns) = 4.306 ns; Loc. = CLKCTRL_G13; Fanout = 30; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.378 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.537 ns) 5.843 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA 5 REG LCFF_X46_Y24_N5 1 " "Info: 5: + IC(1.000 ns) + CELL(0.537 ns) = 5.843 ns; Loc. = LCFF_X46_Y24_N5; Fanout = 1; REG Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.537 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 39.76 % ) " "Info: Total cell delay = 2.323 ns ( 39.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.520 ns ( 60.24 % ) " "Info: Total interconnect delay = 3.520 ns ( 60.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.843 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.843 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.000ns 0.118ns 1.024ns 1.378ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 5.843 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 5.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 17 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/DE2_LCM_Test.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.787 ns) 2.928 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK 3 REG LCFF_X30_Y8_N25 3 " "Info: 3: + IC(1.024 ns) + CELL(0.787 ns) = 2.928 ns; Loc. = LCFF_X30_Y8_N25; Fanout = 3; REG Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.811 ns" { CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.378 ns) + CELL(0.000 ns) 4.306 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK~clkctrl 4 COMB CLKCTRL_G13 30 " "Info: 4: + IC(1.378 ns) + CELL(0.000 ns) = 4.306 ns; Loc. = CLKCTRL_G13; Fanout = 30; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.378 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.537 ns) 5.843 ns I2S_LCM_Config:u4\|mI2S_DATA\[12\] 5 REG LCFF_X46_Y24_N23 1 " "Info: 5: + IC(1.000 ns) + CELL(0.537 ns) = 5.843 ns; Loc. = LCFF_X46_Y24_N23; Fanout = 1; REG Node = 'I2S_LCM_Config:u4\|mI2S_DATA\[12\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.537 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "I2S_LCM_Config.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_LCM_Config.v" 44 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 39.76 % ) " "Info: Total cell delay = 2.323 ns ( 39.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.520 ns ( 60.24 % ) " "Info: Total interconnect delay = 3.520 ns ( 60.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.843 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.843 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } { 0.000ns 0.000ns 0.118ns 1.024ns 1.378ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.843 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.843 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.000ns 0.118ns 1.024ns 1.378ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.843 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.843 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } { 0.000ns 0.000ns 0.118ns 1.024ns 1.378ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "I2S_LCM_Config.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_LCM_Config.v" 44 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 71 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.843 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.843 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.000ns 0.118ns 1.024ns 1.378ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.843 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.843 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } { 0.000ns 0.000ns 0.118ns 1.024ns 1.378ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.725 ns - Longest register register " "Info: - Longest register to register delay is 1.725 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2S_LCM_Config:u4\|mI2S_DATA\[12\] 1 REG LCFF_X46_Y24_N23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X46_Y24_N23; Fanout = 1; REG Node = 'I2S_LCM_Config:u4\|mI2S_DATA\[12\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "I2S_LCM_Config.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_LCM_Config.v" 44 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.309 ns) + CELL(0.150 ns) 0.459 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~370 2 COMB LCCOMB_X46_Y24_N6 1 " "Info: 2: + IC(0.309 ns) + CELL(0.150 ns) = 0.459 ns; Loc. = LCCOMB_X46_Y24_N6; Fanout = 1; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~370'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.459 ns" { I2S_LCM_Config:u4|mI2S_DATA[12] I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 128 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.150 ns) 0.855 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~371 3 COMB LCCOMB_X46_Y24_N10 1 " "Info: 3: + IC(0.246 ns) + CELL(0.150 ns) = 0.855 ns; Loc. = LCCOMB_X46_Y24_N10; Fanout = 1; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~371'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.396 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 128 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.150 ns) 1.252 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~372 4 COMB LCCOMB_X46_Y24_N0 1 " "Info: 4: + IC(0.247 ns) + CELL(0.150 ns) = 1.252 ns; Loc. = LCCOMB_X46_Y24_N0; Fanout = 1; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~372'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.397 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 128 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.150 ns) 1.641 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~375 5 COMB LCCOMB_X46_Y24_N4 1 " "Info: 5: + IC(0.239 ns) + CELL(0.150 ns) = 1.641 ns; Loc. = LCCOMB_X46_Y24_N4; Fanout = 1; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~375'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.389 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 128 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.725 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA 6 REG LCFF_X46_Y24_N5 1 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 1.725 ns; Loc. = LCFF_X46_Y24_N5; Fanout = 1; REG Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "E:/EDA_DESIGN/DE2_LCM_Test/I2S_Controller.v" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.684 ns ( 39.65 % ) " "Info: Total cell delay = 0.684 ns ( 39.65 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.041 ns ( 60.35 % ) " "Info: Total interconnect delay = 1.041 ns ( 60.35 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.725 ns" { I2S_LCM_Config:u4|mI2S_DATA[12] I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.725 ns" { I2S_LCM_Config:u4|mI2S_DATA[12] I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.309ns 0.246ns 0.247ns 0.239ns 0.000ns } { 0.000ns 0.150ns 0.150ns 0.150ns 0.150ns 0.084ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.843 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.843 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.000ns 0.118ns 1.024ns 1.378ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.843 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.843 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } { 0.000ns 0.000ns 0.118ns 1.024ns 1.378ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.725 ns" { I2S_LCM_Config:u4|mI2S_DATA[12] I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.725 ns" { I2S_LCM_Config:u4|mI2S_DATA[12] I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.309ns 0.246ns 0.247ns 0.239ns 0.000ns } { 0.000ns 0.150ns 0.150ns 0.150ns 0.150ns 0.084ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
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