de2_lcm_test.hier_info

NIOS下

|DE2_LCM_Test
CLOCK_27 => ~NO_FANOUT~
CLOCK_50 => CLOCK_50~0.IN2
KEY[0] => KEY[0]~0.IN1
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => ~NO_FANOUT~
SW[0] => ~NO_FANOUT~
SW[1] => ~NO_FANOUT~
SW[2] => ~NO_FANOUT~
SW[3] => ~NO_FANOUT~
SW[4] => ~NO_FANOUT~
SW[5] => ~NO_FANOUT~
SW[6] => ~NO_FANOUT~
SW[7] => ~NO_FANOUT~
SW[8] => ~NO_FANOUT~
SW[9] => ~NO_FANOUT~
SW[10] => ~NO_FANOUT~
SW[11] => ~NO_FANOUT~
SW[12] => ~NO_FANOUT~
SW[13] => ~NO_FANOUT~
SW[14] => ~NO_FANOUT~
SW[15] => ~NO_FANOUT~
SW[16] => ~NO_FANOUT~
SW[17] => ~NO_FANOUT~
SRAM_ADDR[0] <= iSRAM_ADDR[0].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[1] <= iSRAM_ADDR[1].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[2] <= iSRAM_ADDR[2].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[3] <= iSRAM_ADDR[3].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[4] <= iSRAM_ADDR[4].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[5] <= iSRAM_ADDR[5].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[6] <= iSRAM_ADDR[6].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[7] <= iSRAM_ADDR[7].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[8] <= iSRAM_ADDR[8].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[9] <= iSRAM_ADDR[9].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[10] <= iSRAM_ADDR[10].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[11] <= iSRAM_ADDR[11].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[12] <= iSRAM_ADDR[12].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[13] <= iSRAM_ADDR[13].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[14] <= iSRAM_ADDR[14].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[15] <= iSRAM_ADDR[15].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[16] <= iSRAM_ADDR[16].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[17] <= iSRAM_ADDR[17].DB_MAX_OUTPUT_PORT_TYPE
SRAM_UB_N <= <GND>
SRAM_LB_N <= <GND>
SRAM_WE_N <= <VCC>
SRAM_CE_N <= <GND>
SRAM_OE_N <= <GND>
I2C_SDAT <= <UNC>
I2C_SCLK <= <GND>
GPIO_0[0] <= GPIO_0~88
GPIO_0[1] <= GPIO_0~87
GPIO_0[2] <= GPIO_0~86
GPIO_0[3] <= GPIO_0~85
GPIO_0[4] <= GPIO_0~84
GPIO_0[5] <= GPIO_0~83
GPIO_0[6] <= GPIO_0~82
GPIO_0[7] <= GPIO_0~81
GPIO_0[8] <= GPIO_0~80
GPIO_0[9] <= GPIO_0~79
GPIO_0[10] <= GPIO_0~78
GPIO_0[11] <= GPIO_0~77
GPIO_0[12] <= GPIO_0~76
GPIO_0[13] <= GPIO_0~75
GPIO_0[14] <= GPIO_0~74
GPIO_0[15] <= GPIO_0~73
GPIO_0[16] <= GPIO_0~72
GPIO_0[17] <= GPIO_0~71
GPIO_0[18] <= GPIO_0~70
GPIO_0[18] <= GPIO_0~89
GPIO_0[19] <= GPIO_0~68
GPIO_0[19] <= GPIO_0~90
GPIO_0[20] <= GPIO_0~66
GPIO_0[20] <= GPIO_0~91
GPIO_0[21] <= GPIO_0~64
GPIO_0[21] <= GPIO_0~92
GPIO_0[22] <= GPIO_0~62
GPIO_0[22] <= GPIO_0~93
GPIO_0[23] <= GPIO_0~60
GPIO_0[23] <= GPIO_0~94
GPIO_0[24] <= GPIO_0~58
GPIO_0[24] <= GPIO_0~95
GPIO_0[25] <= GPIO_0~56
GPIO_0[25] <= GPIO_0~96
GPIO_0[26] <= GPIO_0~54
GPIO_0[26] <= GPIO_0~97
GPIO_0[27] <= GPIO_0~52
GPIO_0[28] <= GPIO_0~51
GPIO_0[28] <= GPIO_0~98
GPIO_0[29] <= GPIO_0~49
GPIO_0[29] <= GPIO_0~99
GPIO_0[30] <= GPIO_0~47
GPIO_0[30] <= GPIO_0~100
GPIO_0[31] <= GPIO_0~45
GPIO_0[31] <= GPIO_0~101
GPIO_0[32] <= GPIO_0~43
GPIO_0[33] <= GPIO_0~41
GPIO_0[33] <= GPIO_0~102
GPIO_0[34] <= GPIO_0~39
GPIO_0[34] <= GPIO_0~103
GPIO_0[35] <= GPIO_0~37
GPIO_0[35] <= GPIO_0~104


|DE2_LCM_Test|LCM_PLL:u0
inclk0 => sub_wire3[0].IN1
c0 <= altpll:altpll_component.clk


|DE2_LCM_Test|LCM_PLL:u0|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE


|DE2_LCM_Test|I2S_LCM_Config:u4
iCLK => iCLK~0.IN1
iRST_N => iRST_N~0.IN1
I2S_SCLK <= I2S_Controller:u0.I2S_CLK
I2S_SDAT <= I2S_Controller:u0.I2S_DATA
I2S_SCEN <= I2S_Controller:u0.I2S_EN


|DE2_LCM_Test|I2S_LCM_Config:u4|I2S_Controller:u0
iCLK => mI2S_CLK_DIV[15].CLK
iCLK => mI2S_CLK_DIV[14].CLK
iCLK => mI2S_CLK_DIV[13].CLK
iCLK => mI2S_CLK_DIV[12].CLK
iCLK => mI2S_CLK_DIV[11].CLK
iCLK => mI2S_CLK_DIV[10].CLK
iCLK => mI2S_CLK_DIV[9].CLK
iCLK => mI2S_CLK_DIV[8].CLK
iCLK => mI2S_CLK_DIV[7].CLK
iCLK => mI2S_CLK_DIV[6].CLK
iCLK => mI2S_CLK_DIV[5].CLK
iCLK => mI2S_CLK_DIV[4].CLK
iCLK => mI2S_CLK_DIV[3].CLK
iCLK => mI2S_CLK_DIV[2].CLK
iCLK => mI2S_CLK_DIV[1].CLK
iCLK => mI2S_CLK_DIV[0].CLK
iCLK => mI2S_CLK.CLK
iRST => mI2S_CLK_DIV[15].ACLR
iRST => mI2S_CLK_DIV[14].ACLR
iRST => mI2S_CLK_DIV[13].ACLR
iRST => mI2S_CLK_DIV[12].ACLR
iRST => mI2S_CLK_DIV[11].ACLR
iRST => mI2S_CLK_DIV[10].ACLR
iRST => mI2S_CLK_DIV[9].ACLR
iRST => mI2S_CLK_DIV[8].ACLR
iRST => mI2S_CLK_DIV[7].ACLR
iRST => mI2S_CLK_DIV[6].ACLR
iRST => mI2S_CLK_DIV[5].ACLR
iRST => mI2S_CLK_DIV[4].ACLR
iRST => mI2S_CLK_DIV[3].ACLR
iRST => mI2S_CLK_DIV[2].ACLR
iRST => mI2S_CLK_DIV[1].ACLR
iRST => mI2S_CLK_DIV[0].ACLR
iRST => mSCLK.ACLR
iRST => mI2S_CLK.ACLR
iRST => mSDATA.ACLR
iRST => mACK.ACLR
iRST => mST[4].ACLR
iRST => mST[3].ACLR
iRST => mST[2].ACLR
iRST => mST[1].ACLR
iRST => mST[0].ACLR
iRST => always1~1.ACLR
iRST => mSEN.PRESET
iDATA[0] => Mux0.IN4
iDATA[1] => Mux0.IN5
iDATA[2] => Mux0.IN6
iDATA[3] => Mux0.IN7
iDATA[4] => Mux0.IN8
iDATA[5] => Mux0.IN9
iDATA[6] => Mux0.IN10
iDATA[7] => Mux0.IN11
iDATA[8] => Mux0.IN12
iDATA[9] => Mux0.IN13
iDATA[10] => Mux0.IN14
iDATA[11] => Mux0.IN15
iDATA[12] => Mux0.IN16
iDATA[13] => Mux0.IN17
iDATA[14] => Mux0.IN18
iDATA[15] => Mux0.IN19
iSTR => mST~5.OUTPUTSELECT
iSTR => mST~6.OUTPUTSELECT
iSTR => mST~7.OUTPUTSELECT
iSTR => mST~8.OUTPUTSELECT
iSTR => mST~9.OUTPUTSELECT
iSTR => mSEN~3.OUTPUTSELECT
iSTR => mSCLK~3.OUTPUTSELECT
iSTR => mACK~2.OUTPUTSELECT
iSTR => always1~2.IN0
iSTR => always1~1.DATAIN
oACK <= mACK.DB_MAX_OUTPUT_PORT_TYPE
oRDY <= Equal3.DB_MAX_OUTPUT_PORT_TYPE
oCLK <= mI2S_CLK.DB_MAX_OUTPUT_PORT_TYPE
I2S_EN <= mSEN.DB_MAX_OUTPUT_PORT_TYPE
I2S_DATA <= I2S_DATA~1
I2S_CLK <= I2S_CLK~0.DB_MAX_OUTPUT_PORT_TYPE