de2_lcm_test.v

NIOS下

module DE2_LCM_Test
	(
		////////////////////	Clock Input	 	////////////////////	 
		CLOCK_27,						//	27 MHz
		CLOCK_50,						//	50 MHz
		////////////////////	Push Button		////////////////////
		KEY,							//	Pushbutton[3:0]
		////////////////////	DPDT Switch		////////////////////
		SW,								//	Toggle Switch[17:0]
	    ////////////////////	SRAM Interface		////////////////
		SRAM_DQ,						//	SRAM Data bus 16 Bits
		SRAM_ADDR,						//	SRAM Address bus 18 Bits
		SRAM_UB_N,						//	SRAM High-byte Data Mask 
		SRAM_LB_N,						//	SRAM Low-byte Data Mask 
		SRAM_WE_N,						//	SRAM Write Enable
		SRAM_CE_N,						//	SRAM Chip Enable
		SRAM_OE_N,						//	SRAM Output Enable
		////////////////////	I2C		////////////////////////////
		I2C_SDAT,						//	I2C Data
		I2C_SCLK,						//	I2C Clock
		////////////////////	GPIO	////////////////////////////
		GPIO_0,							//	GPIO_0 CONNECT TO LCM
	);

////////////////////////	Clock Input	 	////////////////////////
input			CLOCK_27;				//	27 MHz
input			CLOCK_50;				//	50 MHz
////////////////////////	Push Button		////////////////////////
input	[3:0]	KEY;					//	Pushbutton[3:0]
////////////////////////	DPDT Switch		////////////////////////
input	[17:0]	SW;						//	Toggle Switch[17:0]
////////////////////////	SRAM Interface	////////////////////////
inout	[15:0]	SRAM_DQ;				//	SRAM Data bus 16 Bits
output	[17:0]	SRAM_ADDR;				//	SRAM Address bus 18 Bits
output			SRAM_UB_N;				//	SRAM High-byte Data Mask 
output			SRAM_LB_N;				//	SRAM Low-byte Data Mask 
output			SRAM_WE_N;				//	SRAM Write Enable
output			SRAM_CE_N;				//	SRAM Chip Enable
output			SRAM_OE_N;				//	SRAM Output Enable
////////////////////////	I2C		////////////////////////////////
inout			I2C_SDAT;				//	I2C Data
output			I2C_SCLK;				//	I2C Clock
inout	[35:0]	GPIO_0;					//	GPIO Connection 0
assign	GPIO_0		=	36'hzzzzzzzzz;

wire	[7:0]	LCM_DATA;		//	LCM Data 8 Bits
wire			LCM_GRST;		//	LCM Global Reset	
wire			LCM_SHDB;		//	LCM Sleep Mode
wire			LCM_DCLK;		//	LCM Clcok
wire			LCM_HSYNC;		//	LCM HSYNC
wire			LCM_VSYNC;		//	LCM	VSYNC
wire			LCM_SCLK;		//	LCM I2C Clock
wire			LCM_SDAT;		//	LCM I2C Data
wire			LCM_SCEN;		//	LCM I2C Enable

assign	GPIO_0[18]	=	LCM_DATA[6];
assign	GPIO_0[19]	=	LCM_DATA[7];
assign	GPIO_0[20]	=	LCM_DATA[4];
assign	GPIO_0[21]	=	LCM_DATA[5];
assign	GPIO_0[22]	=	LCM_DATA[2];
assign	GPIO_0[23]	=	LCM_DATA[3];
assign	GPIO_0[24]	=	LCM_DATA[0];
assign	GPIO_0[25]	=	LCM_DATA[1];
assign	GPIO_0[26]	=	LCM_VSYNC;
assign	GPIO_0[28]	=	LCM_SCLK;
assign	GPIO_0[29]	=	LCM_DCLK;
assign	GPIO_0[30]	=	LCM_GRST;
assign	GPIO_0[31]	=	LCM_SHDB;
assign	GPIO_0[33]	=	LCM_SCEN;
assign	GPIO_0[34]	=	LCM_SDAT;
assign	GPIO_0[35]	=	LCM_HSYNC;

assign	LCM_GRST	=	KEY[0];
assign	TD_RESET	=	KEY[0];
assign	LCM_DCLK	=	~CLK_25;
assign	LCM_SHDB	=	1'b1;

assign	SRAM_UB_N	=	1'b0;
assign	SRAM_LB_N	=	1'b0;
assign  SRAM_OE_N   =   1'b0;
assign  SRAM_CE_N   =   1'b0;
assign  SRAM_WE_N   =   1'b1;
assign  SRAM_ADDR   =   iSRAM_ADDR;

wire			iCLK;
wire			iRST_N;
reg		[10:0]	H_Cont;
reg		[10:0]	V_Cont;
reg		[7:0]	Tmp_DATA;
reg		[7:0]	IMAG_DATA;
reg				oVGA_H_SYNC;
reg				oVGA_V_SYNC;
reg				CLK_25;
wire	[1:0]	mSEL;
reg		[17:0]	iSRAM_ADDR;


assign	iCLK		=	CLK_25;
assign	iRST_N		=	KEY[0];
assign	LCM_VSYNC	=	oVGA_V_SYNC;
assign	LCM_HSYNC	=	oVGA_H_SYNC;

assign	LCM_DATA	=	IMAG_DATA;

//	Horizontal Parameter	( Pixel )
parameter	H_SYNC_CYC	=	1;
parameter	H_SYNC_BACK	=	151;
parameter	H_SYNC_ACT	=	960;
parameter	H_SYNC_FRONT=	59;
parameter	H_SYNC_TOTAL=	1171;
//	Virtical Parameter		( Line )
parameter	V_SYNC_CYC	=	1;
parameter	V_SYNC_BACK	=	13;
parameter	V_SYNC_ACT	=	240;
parameter	V_SYNC_FRONT=	8;
parameter	V_SYNC_TOTAL=	262;

LCM_PLL 	u0	(	.inclk0(CLOCK_50),.c0(CLK_25));

reg		[1:0]	RGB_SEL;

always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		Tmp_DATA	<=	8'h00;
		RGB_SEL		<=	2'b00;	
	end
	else
	begin
		if(	H_Cont>H_SYNC_BACK && H_Cont<(H_SYNC_TOTAL-H_SYNC_FRONT))
		begin
			if(RGB_SEL<2'b10)
			RGB_SEL	<=	RGB_SEL+1'b1;
			else
			RGB_SEL	<=	2'b00;
			Tmp_DATA<=	Tmp_DATA+1'b1;
		end
		else
		begin
			RGB_SEL	<=	2'b00;
			Tmp_DATA<=	8'h00;	
		end
	end
end

//	H_Sync Generator, Ref. 25.175 MHz Clock
always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		H_Cont		<=	0;
		oVGA_H_SYNC	<=	0;
	end
	else
	begin
		//	H_Sync Counter
		if( H_Cont < H_SYNC_TOTAL )
		H_Cont	<=	H_Cont+1;
		else
		H_Cont	<=	0;
		//	H_Sync Generator
		if( H_Cont < H_SYNC_CYC )
		oVGA_H_SYNC	<=	0;
		else
		oVGA_H_SYNC	<=	1;
	end
end

//	V_Sync Generator, Ref. H_Sync
always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	 begin
		V_Cont		<=	0;
		oVGA_V_SYNC	<=	0;
	 end
	else
	 begin
		//	When H_Sync Re-start
		if(H_Cont==0)
		begin
			//	V_Sync Counter
			if( V_Cont < V_SYNC_TOTAL )
			V_Cont	<=	V_Cont+1;
			else
			V_Cont	<=	0;
			//	V_Sync Generator
			if(	V_Cont < V_SYNC_CYC )
			oVGA_V_SYNC	<=	0;
			else
			oVGA_V_SYNC	<=	1;
		end
	 end
end

//	Image data read.
always@(posedge iCLK )
begin
  iSRAM_ADDR<=(((V_Cont-15)*480) + (H_Cont>>1)-74);
   if(H_Cont[0]==1)
   IMAG_DATA<=SRAM_DQ[7:0];
   else
   IMAG_DATA<=SRAM_DQ[15:8];
end


I2S_LCM_Config 	u4	(	//	Host Side
						.iCLK(CLOCK_50),
						.iRST_N(KEY[0]),
						//	I2C Side
						.I2S_SCLK(LCM_SCLK),
						.I2S_SDAT(LCM_SDAT),
						.I2S_SCEN(LCM_SCEN)	);
endmodule