de2_lcm_test.tan.rpt

NIOS下

; Total number of failed paths                            ;           ;                                  ;                                  ;                                            ;                                            ;                                          ;                                          ; 0            ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------+--------------------------------------------+------------------------------------------+------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                           ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                          ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; LCM_PLL:u0|altpll:altpll_component|_clk0 ;                    ; PLL output ; 18.42 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 7                     ; 19                  ; -2.358 ns ;              ;
; CLOCK_50                                 ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'LCM_PLL:u0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+------------+----------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From       ; To             ; From Clock                               ; To Clock                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------+----------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 45.095 ns                               ; 108.81 MHz ( period = 9.190 ns )                    ; V_Cont[0]  ; iSRAM_ADDR[17] ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.089 ns                 ; 8.994 ns                ;
; 45.232 ns                               ; 110.46 MHz ( period = 9.053 ns )                    ; V_Cont[1]  ; iSRAM_ADDR[17] ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.089 ns                 ; 8.857 ns                ;
; 45.282 ns                               ; 111.07 MHz ( period = 9.003 ns )                    ; V_Cont[2]  ; iSRAM_ADDR[17] ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.089 ns                 ; 8.807 ns                ;
; 45.317 ns                               ; 111.51 MHz ( period = 8.968 ns )                    ; V_Cont[0]  ; iSRAM_ADDR[16] ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.089 ns                 ; 8.772 ns                ;
; 45.383 ns                               ; 112.33 MHz ( period = 8.902 ns )                    ; V_Cont[3]  ; iSRAM_ADDR[17] ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.089 ns                 ; 8.706 ns                ;
; 45.415 ns                               ; 112.74 MHz ( period = 8.870 ns )                    ; V_Cont[4]  ; iSRAM_ADDR[17] ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.089 ns                 ; 8.674 ns                ;
; 45.433 ns                               ; 112.97 MHz ( period = 8.852 ns )                    ; V_Cont[0]  ; iSRAM_ADDR[15] ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.089 ns                 ; 8.656 ns                ;
; 45.454 ns                               ; 113.24 MHz ( period = 8.831 ns )                    ; V_Cont[1]  ; iSRAM_ADDR[16] ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.089 ns                 ; 8.635 ns                ;
; 45.504 ns                               ; 113.88 MHz ( period = 8.781 ns )                    ; V_Cont[2]  ; iSRAM_ADDR[16] ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.089 ns                 ; 8.585 ns                ;
; 45.533 ns                               ; 114.26 MHz ( period = 8.752 ns )                    ; V_Cont[0]  ; iSRAM_ADDR[14] ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.089 ns                 ; 8.556 ns                ;
; 45.570 ns                               ; 114.74 MHz ( period = 8.715 ns )                    ; V_Cont[1]  ; iSRAM_ADDR[15] ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.089 ns                 ; 8.519 ns                ;