de2_lcm_test.tan.rpt

NIOS下

Timing Analyzer report for DE2_LCM_Test
Mon Jul 30 10:37:17 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'LCM_PLL:u0|altpll:altpll_component|_clk0'
  6. Clock Setup: 'CLOCK_50'
  7. Clock Hold: 'LCM_PLL:u0|altpll:altpll_component|_clk0'
  8. Clock Hold: 'CLOCK_50'
  9. tsu
 10. tco
 11. tpd
 12. th
 13. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                  ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------+--------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Type                                                    ; Slack     ; Required Time                    ; Actual Time                      ; From                                       ; To                                         ; From Clock                               ; To Clock                                 ; Failed Paths ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------+--------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Worst-case tsu                                          ; N/A       ; None                             ; 6.443 ns                         ; SRAM_DQ[0]                                 ; IMAG_DATA[0]                               ; --                                       ; CLOCK_50                                 ; 0            ;
; Worst-case tco                                          ; N/A       ; None                             ; 12.333 ns                        ; I2S_LCM_Config:u4|I2S_Controller:u0|mST[2] ; GPIO_0[34]                                 ; CLOCK_50                                 ; --                                       ; 0            ;
; Worst-case tpd                                          ; N/A       ; None                             ; 8.345 ns                         ; KEY[0]                                     ; GPIO_0[30]                                 ; --                                       ; --                                       ; 0            ;
; Worst-case th                                           ; N/A       ; None                             ; -1.546 ns                        ; KEY[0]                                     ; I2S_LCM_Config:u4|mI2S_DATA[12]            ; --                                       ; CLOCK_50                                 ; 0            ;
; Clock Setup: 'CLOCK_50'                                 ; 8.061 ns  ; 50.00 MHz ( period = 20.000 ns ) ; 257.86 MHz ( period = 3.878 ns ) ; I2S_LCM_Config:u4|mI2S_DATA[12]            ; I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA ; CLOCK_50                                 ; CLOCK_50                                 ; 0            ;
; Clock Setup: 'LCM_PLL:u0|altpll:altpll_component|_clk0' ; 45.095 ns ; 18.42 MHz ( period = 54.285 ns ) ; 108.81 MHz ( period = 9.190 ns ) ; V_Cont[0]                                  ; iSRAM_ADDR[17]                             ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'LCM_PLL:u0|altpll:altpll_component|_clk0'  ; 0.391 ns  ; 18.42 MHz ( period = 54.285 ns ) ; N/A                              ; oVGA_V_SYNC                                ; oVGA_V_SYNC                                ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'CLOCK_50'                                  ; 0.391 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; I2S_LCM_Config:u4|LUT_INDEX[0]             ; I2S_LCM_Config:u4|LUT_INDEX[0]             ; CLOCK_50                                 ; CLOCK_50                                 ; 0            ;