generalfifo.txt

通用FIFO的VHDL编程 字深和字长可以自己设计

LIBRARY IEEE;0
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;

ENTITY fifoxbyy IS
	GENERIC(deep:integer:=53;
	        wide:integer:=8);
	PORT(clk,rst:IN std_logic;
	     rd,wr:IN std_logic;
	     rdinc,wrinc:IN std_logic;
	     rdptrclr,wrptrclr:IN std_logic;
	     data_in:IN std_logic_vector(wide-1 DOWNTO 0);
	     data_out:OUT std_logic_vector(wide-1 DOWNTO 0));
END fifoxbyy;
	
ARCHITECTURE rtl OF fifoxbyy IS
	CONSTANT zero_tmp1:integer:=0;
	CONSTANT zero_tmp2:std_logic_vector(wide-1 DOWNTO 0):=(OTHERS=>'0');
	SUBTYPE word IS std_logic_vector(wide-1 DOWNTO 0);
	TYPE fifo_array IS ARRAY(deep-1 DOWNTO 0)OF word;
	SIGNAL fifo:fifo_array;
	SIGNAL rdptr,wrptr:integer RANGE 0 TO deep-1;
	SIGNAL en:std_logic_vector(deep-1 DOWNTO 0);
	SIGNAL dmuxout:std_logic_vector(wide-1 DOWNTO 0);
BEGIN
	--读指针操作
	read_count:PROCESS(rst,clk)
	BEGIN
		IF(rst='1')THEN
			rdptr<=zero_tmp1;
		ELSIF(clk'event AND clk='1')THEN
			IF(rdptrclr='1')THEN
				rdptr<=zero_tmp1;
			ELSIF(rdinc='1')THEN
				IF(rdptr=deep-1)THEN
					rdptr<=zero_tmp1;
				ELSE
					rdptr<=rdptr+1;
				END IF;
			END IF;
		END IF;
	END PROCESS read_count;
	--写指针操作
	write_count:PROCESS(rst,clk)
	BEGIN
		IF(rst='1')THEN
			wrptr<=zero_tmp1;
		ELSIF(clk'event AND clk='1')THEN
			IF(wrptrclr='1')THEN
				wrptr<=zero_tmp1;
			ELSIF(wrinc='1')THEN
				IF(wrptr=deep-1)THEN
					wrptr<=zero_tmp1;
					ELSE
						wrptr<=wrptr+1;
					END IF;
				END IF;
			END IF;
		END PROCESS	 write_count;
	--FIFO写操作
	reg_write:PROCESS(rst,clk)
	BEGIN 
		IF(rst='1')THEN
			FOR i IN deep-1 DOWNTO 0 LOOP
				fifo(i)<=zero_tmp2;
			END LOOP;
		ELSIF(clk'event AND clk='1')THEN
			IF(wr='1')THEN
				fifo(wrptr)<=data_in;
			END IF;
		END IF;
	END PROCESS reg_write;
	--输出数据多路选择齐
	dmuxout<=fifo(rdptr);
	--三态输出
	threestate_output:PROCESS(rd,dmuxout)
	BEGIN
		IF(rd='1')THEN
			data_out<=dmuxout;
		ELSE
			data_out<=zero_tmp2;
		END IF;
	END PROCESS threestate_output;
END rtl;