fir.map.qmsg

来自「我自己用VHDL语言编的16阶FIR数字滤波器」· QMSG 代码 · 共 89 行 · 第 1/3 页

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult45.vhd(27) " "Warning (10492): VHDL Process Statement warning at mult45.vhd(27): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult45.vhd" "" { Text "G:/vhdltext/fir/mult45.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult45.vhd(30) " "Warning (10492): VHDL Process Statement warning at mult45.vhd(30): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult45.vhd" "" { Text "G:/vhdltext/fir/mult45.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult45.vhd(30) " "Warning (10492): VHDL Process Statement warning at mult45.vhd(30): signal \"s2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult45.vhd" "" { Text "G:/vhdltext/fir/mult45.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult45.vhd(30) " "Warning (10492): VHDL Process Statement warning at mult45.vhd(30): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult45.vhd" "" { Text "G:/vhdltext/fir/mult45.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add161717 add161717:inst36 " "Info: Elaborating entity \"add161717\" for hierarchy \"add161717:inst36\"" {  } { { "fir.bdf" "inst36" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1016 2152 2312 1112 "inst36" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult92 mult92:inst31 " "Info: Elaborating entity \"mult92\" for hierarchy \"mult92:inst31\"" {  } { { "fir.bdf" "inst31" { Schematic "G:/vhdltext/fir/fir.bdf" { { 784 2016 2112 936 "inst31" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult92.vhd(31) " "Warning (10492): VHDL Process Statement warning at mult92.vhd(31): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult92.vhd" "" { Text "G:/vhdltext/fir/mult92.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult92.vhd(31) " "Warning (10492): VHDL Process Statement warning at mult92.vhd(31): signal \"s2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult92.vhd" "" { Text "G:/vhdltext/fir/mult92.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult92.vhd(31) " "Warning (10492): VHDL Process Statement warning at mult92.vhd(31): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult92.vhd" "" { Text "G:/vhdltext/fir/mult92.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s4 mult92.vhd(31) " "Warning (10492): VHDL Process Statement warning at mult92.vhd(31): signal \"s4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult92.vhd" "" { Text "G:/vhdltext/fir/mult92.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult92.vhd(34) " "Warning (10492): VHDL Process Statement warning at mult92.vhd(34): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult92.vhd" "" { Text "G:/vhdltext/fir/mult92.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult92.vhd(34) " "Warning (10492): VHDL Process Statement warning at mult92.vhd(34): signal \"s2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult92.vhd" "" { Text "G:/vhdltext/fir/mult92.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult92.vhd(34) " "Warning (10492): VHDL Process Statement warning at mult92.vhd(34): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult92.vhd" "" { Text "G:/vhdltext/fir/mult92.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s4 mult92.vhd(34) " "Warning (10492): VHDL Process Statement warning at mult92.vhd(34): signal \"s4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult92.vhd" "" { Text "G:/vhdltext/fir/mult92.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult212 mult212:inst25 " "Info: Elaborating entity \"mult212\" for hierarchy \"mult212:inst25\"" {  } { { "fir.bdf" "inst25" { Schematic "G:/vhdltext/fir/fir.bdf" { { 800 2272 2368 952 "inst25" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult212.vhd(29) " "Warning (10492): VHDL Process Statement warning at mult212.vhd(29): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult212.vhd" "" { Text "G:/vhdltext/fir/mult212.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult212.vhd(29) " "Warning (10492): VHDL Process Statement warning at mult212.vhd(29): signal \"s2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult212.vhd" "" { Text "G:/vhdltext/fir/mult212.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult212.vhd(29) " "Warning (10492): VHDL Process Statement warning at mult212.vhd(29): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult212.vhd" "" { Text "G:/vhdltext/fir/mult212.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s4 mult212.vhd(29) " "Warning (10492): VHDL Process Statement warning at mult212.vhd(29): signal \"s4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult212.vhd" "" { Text "G:/vhdltext/fir/mult212.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult212.vhd(32) " "Warning (10492): VHDL Process Statement warning at mult212.vhd(32): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult212.vhd" "" { Text "G:/vhdltext/fir/mult212.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult212.vhd(32) " "Warning (10492): VHDL Process Statement warning at mult212.vhd(32): signal \"s2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult212.vhd" "" { Text "G:/vhdltext/fir/mult212.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult212.vhd(32) " "Warning (10492): VHDL Process Statement warning at mult212.vhd(32): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult212.vhd" "" { Text "G:/vhdltext/fir/mult212.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s4 mult212.vhd(32) " "Warning (10492): VHDL Process Statement warning at mult212.vhd(32): signal \"s4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult212.vhd" "" { Text "G:/vhdltext/fir/mult212.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mult212:inst25\|Dout\[0\] data_in GND " "Warning: Reduced register \"mult212:inst25\|Dout\[0\]\" with stuck data_in port to stuck value GND" {  } { { "mult212.vhd" "" { Text "G:/vhdltext/fir/mult212.vhd" 38 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mult92:inst31\|Dout\[0\] data_in GND " "Warning: Reduced register \"mult92:inst31\|Dout\[0\]\" with stuck data_in port to stuck value GND" {  } { { "mult92.vhd" "" { Text "G:/vhdltext/fir/mult92.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add161717:inst36\|Dout\[0\] data_in GND " "Warning: Reduced register \"add161717:inst36\|Dout\[0\]\" with stuck data_in port to stuck value GND" {  } { { "add161717.vhd" "" { Text "G:/vhdltext/fir/add161717.vhd" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "615 " "Info: Implemented 615 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "594 " "Info: Implemented 594 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 47 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 47 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 03 12:06:42 2008 " "Info: Processing ended: Sat May 03 12:06:42 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Info: Elapsed time: 00:00:16" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}