fir.map.qmsg

来自「我自己用VHDL语言编的16阶FIR数字滤波器」· QMSG 代码 · 共 89 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 03 12:06:27 2008 " "Info: Processing started: Sat May 03 12:06:27 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fir -c fir " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fir -c fir" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add111414.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file add111414.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add111414-a " "Info: Found design unit 1: add111414-a" {  } { { "add111414.vhd" "" { Text "G:/vhdltext/fir/add111414.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add111414 " "Info: Found entity 1: add111414" {  } { { "add111414.vhd" "" { Text "G:/vhdltext/fir/add111414.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add121414.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file add121414.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add121414-a " "Info: Found design unit 1: add121414-a" {  } { { "add121414.vhd" "" { Text "G:/vhdltext/fir/add121414.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add121414 " "Info: Found entity 1: add121414" {  } { { "add121414.vhd" "" { Text "G:/vhdltext/fir/add121414.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add141415.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file add141415.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add141415-a " "Info: Found design unit 1: add141415-a" {  } { { "add141415.vhd" "" { Text "G:/vhdltext/fir/add141415.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add141415 " "Info: Found entity 1: add141415" {  } { { "add141415.vhd" "" { Text "G:/vhdltext/fir/add141415.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/vhdltext/fir/add141710.vhd " "Warning: Can't analyze file -- file G:/vhdltext/fir/add141710.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add151415.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file add151415.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add151415-a " "Info: Found design unit 1: add151415-a" {  } { { "add151415.vhd" "" { Text "G:/vhdltext/fir/add151415.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add151415 " "Info: Found entity 1: add151415" {  } { { "add151415.vhd" "" { Text "G:/vhdltext/fir/add151415.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add161717.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file add161717.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add161717-a " "Info: Found design unit 1: add161717-a" {  } { { "add161717.vhd" "" { Text "G:/vhdltext/fir/add161717.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add161717 " "Info: Found entity 1: add161717" {  } { { "add161717.vhd" "" { Text "G:/vhdltext/fir/add161717.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add9910.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file add9910.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add9910-a " "Info: Found design unit 1: add9910-a" {  } { { "add9910.vhd" "" { Text "G:/vhdltext/fir/add9910.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add9910 " "Info: Found entity 1: add9910" {  } { { "add9910.vhd" "" { Text "G:/vhdltext/fir/add9910.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dff9.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dff9.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dff9-a " "Info: Found design unit 1: dff9-a" {  } { { "dff9.vhd" "" { Text "G:/vhdltext/fir/dff9.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dff9 " "Info: Found entity 1: dff9" {  } { { "dff9.vhd" "" { Text "G:/vhdltext/fir/dff9.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult19.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mult19.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mult19-a " "Info: Found design unit 1: mult19-a" {  } { { "mult19.vhd" "" { Text "G:/vhdltext/fir/mult19.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mult19 " "Info: Found entity 1: mult19" {  } { { "mult19.vhd" "" { Text "G:/vhdltext/fir/mult19.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult212.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mult212.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mult212-a " "Info: Found design unit 1: mult212-a" {  } { { "mult212.vhd" "" { Text "G:/vhdltext/fir/mult212.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mult212 " "Info: Found entity 1: mult212" {  } { { "mult212.vhd" "" { Text "G:/vhdltext/fir/mult212.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult25.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mult25.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mult25-a " "Info: Found design unit 1: mult25-a" {  } { { "mult25.vhd" "" { Text "G:/vhdltext/fir/mult25.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mult25 " "Info: Found entity 1: mult25" {  } { { "mult25.vhd" "" { Text "G:/vhdltext/fir/mult25.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult29.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mult29.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mult29-a " "Info: Found design unit 1: mult29-a" {  } { { "mult29.vhd" "" { Text "G:/vhdltext/fir/mult29.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mult29 " "Info: Found entity 1: mult29" {  } { { "mult29.vhd" "" { Text "G:/vhdltext/fir/mult29.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult3.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mult3.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mult3-a " "Info: Found design unit 1: mult3-a" {  } { { "mult3.vhd" "" { Text "G:/vhdltext/fir/mult3.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mult3 " "Info: Found entity 1: mult3" {  } { { "mult3.vhd" "" { Text "G:/vhdltext/fir/mult3.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult45.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mult45.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mult45-a " "Info: Found design unit 1: mult45-a" {  } { { "mult45.vhd" "" { Text "G:/vhdltext/fir/mult45.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mult45 " "Info: Found entity 1: mult45" {  } { { "mult45.vhd" "" { Text "G:/vhdltext/fir/mult45.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult6.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mult6.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mult6-a " "Info: Found design unit 1: mult6-a" {  } { { "mult6.vhd" "" { Text "G:/vhdltext/fir/mult6.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mult6 " "Info: Found entity 1: mult6" {  } { { "mult6.vhd" "" { Text "G:/vhdltext/fir/mult6.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult92.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mult92.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mult92-a " "Info: Found design unit 1: mult92-a" {  } { { "mult92.vhd" "" { Text "G:/vhdltext/fir/mult92.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mult92 " "Info: Found entity 1: mult92" {  } { { "mult92.vhd" "" { Text "G:/vhdltext/fir/mult92.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sub121414.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sub121414.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sub121414-a " "Info: Found design unit 1: sub121414-a" {  } { { "sub121414.vhd" "" { Text "G:/vhdltext/fir/sub121414.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sub121414 " "Info: Found entity 1: sub121414" {  } { { "sub121414.vhd" "" { Text "G:/vhdltext/fir/sub121414.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sub171517.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sub171517.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sub171517-a " "Info: Found design unit 1: sub171517-a" {  } { { "sub171517.vhd" "" { Text "G:/vhdltext/fir/sub171517.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sub171517 " "Info: Found entity 1: sub171517" {  } { { "sub171517.vhd" "" { Text "G:/vhdltext/fir/sub171517.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file fir.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 fir " "Info: Found entity 1: fir" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fir " "Info: Elaborating entity \"fir\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "add151710.vhd 2 1 " "Warning: Using design file add151710.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add151710-a " "Info: Found design unit 1: add151710-a" {  } { { "add151710.vhd" "" { Text "G:/vhdltext/fir/add151710.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add151710 " "Info: Found entity 1: add151710" {  } { { "add151710.vhd" "" { Text "G:/vhdltext/fir/add151710.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add151710 add151710:inst19 " "Info: Elaborating entity \"add151710\" for hierarchy \"add151710:inst19\"" {  } { { "fir.bdf" "inst19" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1320 1288 1384 1480 "inst19" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add141415 add141415:inst37 " "Info: Elaborating entity \"add141415\" for hierarchy \"add141415:inst37\"" {  } { { "fir.bdf" "inst37" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1208 688 848 1304 "inst37" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add111414 add111414:inst34 " "Info: Elaborating entity \"add111414\" for hierarchy \"add111414:inst34\"" {  } { { "fir.bdf" "inst34" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1000 1032 1192 1096 "inst34" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult3 mult3:inst28 " "Info: Elaborating entity \"mult3\" for hierarchy \"mult3:inst28\"" {  } { { "fir.bdf" "inst28" { Schematic "G:/vhdltext/fir/fir.bdf" { { 776 1208 1304 928 "inst28" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult3.vhd(20) " "Warning (10492): VHDL Process Statement warning at mult3.vhd(20): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult3.vhd" "" { Text "G:/vhdltext/fir/mult3.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult3.vhd(23) " "Warning (10492): VHDL Process Statement warning at mult3.vhd(23): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult3.vhd" "" { Text "G:/vhdltext/fir/mult3.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}