fir.fit.qmsg

我自己用VHDL语言编的16阶FIR数字滤波器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 03 12:06:46 2008 " "Info: Processing started: Sat May 03 12:06:46 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off fir -c fir " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fir -c fir" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "fir EP1C3T100C6 " "Info: Selected device EP1C3T100C6 for design \"fir\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" {  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFIOMGR_PINS_MISSING_LOCATION_INFO" "21 21 " "Info: No exact pin location assignment(s) for 21 pins of 21 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Dout\[9\] " "Info: Pin Dout\[9\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1488 1608 1784 1504 "Dout\[9..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Dout\[9\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[9] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Dout\[8\] " "Info: Pin Dout\[8\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1488 1608 1784 1504 "Dout\[9..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Dout\[8\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[8] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Dout\[7\] " "Info: Pin Dout\[7\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1488 1608 1784 1504 "Dout\[9..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Dout\[7\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Dout\[6\] " "Info: Pin Dout\[6\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1488 1608 1784 1504 "Dout\[9..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Dout\[6\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[6] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Dout\[5\] " "Info: Pin Dout\[5\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1488 1608 1784 1504 "Dout\[9..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Dout\[5\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Dout\[4\] " "Info: Pin Dout\[4\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1488 1608 1784 1504 "Dout\[9..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Dout\[4\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Dout\[3\] " "Info: Pin Dout\[3\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1488 1608 1784 1504 "Dout\[9..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Dout\[3\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Dout\[2\] " "Info: Pin Dout\[2\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1488 1608 1784 1504 "Dout\[9..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Dout\[2\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Dout\[1\] " "Info: Pin Dout\[1\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1488 1608 1784 1504 "Dout\[9..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Dout\[1\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Dout\[0\] " "Info: Pin Dout\[0\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1488 1608 1784 1504 "Dout\[9..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Dout\[0\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Dout[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 128 408 576 144 "clk" "" } { 144 2056 2088 160 "clk" "" } { 152 2288 2320 168 "clk" "" } { 144 1616 1648 160 "clk" "" } { 144 1392 1424 160 "clk" "" } { 136 1144 1176 152 "clk" "" } { 136 936 960 152 "clk" "" } { 376 2280 2304 392 "clk" "" } { 376 2544 2568 392 "clk" "" } { 368 2000 2024 384 "clk" "" } { 360 1688 1712 376 "clk" "" } { 360 1440 1464 376 "clk" "" } { 360 1152 1176 376 "clk" "" } { 360 864 896 376 "clk" "" } { 360 608 640 376 "clk" "" } { 756 360 376 784 "clk" "" } { 752 696 712 784 "clk" "" } { 752 968 984 784 "clk" "" } { 744 1256 1272 776 "clk" "" } { 760 1792 1808 792 "clk" "" } { 752 2064 2080 784 "clk" "" } { 760 2320 2336 800 "clk" "" } { 1024 416 440 1040 "clk" "" } { 1016 1016 1032 1032 "clk" "" } { 744 1496 1512 784 "clk" "" } { 1032 1536 1552 1048 "clk" "" } { 1224 656 688 1240 "clk" "" } { 1192 1784 1808 1208 "clk" "" } { 1292 1336 1352 1320 "clk" "" } { 1032 2128 2152 1048 "clk" "" } { 616 904 928 632 "clk" "" } { 600 1168 1190 616 "clk" "" } { 600 1424 1456 616 "clk" "" } { 616 1728 1750 632 "clk" "" } { 616 1968 1992 632 "clk" "" } { 648 2240 2264 664 "clk" "" } { 616 2488 2520 632 "clk" "" } { 144 1840 1872 160 "clk" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clear " "Info: Pin clear not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 160 408 576 176 "clear" "" } { 160 2056 2089 176 "clear" "" } { 168 2288 2322 184 "clear" "" } { 160 1848 1876 176 "clear" "" } { 160 1616 1648 176 "clear" "" } { 160 1392 1426 176 "clear" "" } { 152 1144 1176 168 "clear" "" } { 152 936 967 168 "clear" "" } { 632 904 935 648 "clear" "" } { 616 1168 1199 632 "clear" "" } { 616 1424 1456 632 "clear" "" } { 640 1728 1751 652 "clear" "" } { 632 1968 1999 648 "clear" "" } { 664 2240 2271 680 "clear" "" } { 632 2488 2520 648 "clear" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clear" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clear } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clear } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Din\[8\] " "Info: Pin Din\[8\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 192 408 576 208 "Din\[8..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Din\[8\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[8] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Din\[7\] " "Info: Pin Din\[7\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 192 408 576 208 "Din\[8..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Din\[7\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Din\[4\] " "Info: Pin Din\[4\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 192 408 576 208 "Din\[8..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Din\[4\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Din\[5\] " "Info: Pin Din\[5\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 192 408 576 208 "Din\[8..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Din\[5\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Din\[6\] " "Info: Pin Din\[6\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 192 408 576 208 "Din\[8..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Din\[6\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[6] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Din\[2\] " "Info: Pin Din\[2\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 192 408 576 208 "Din\[8..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Din\[2\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Din\[3\] " "Info: Pin Din\[3\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 192 408 576 208 "Din\[8..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Din\[3\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Din\[1\] " "Info: Pin Din\[1\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 192 408 576 208 "Din\[8..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Din\[1\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Din\[0\] " "Info: Pin Din\[0\] not assigned to an exact location on the device" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 192 408 576 208 "Din\[8..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Din\[0\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 10 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 10" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 128 408 576 144 "clk" "" } { 144 2056 2088 160 "clk" "" } { 152 2288 2320 168 "clk" "" } { 144 1616 1648 160 "clk" "" } { 144 1392 1424 160 "clk" "" } { 136 1144 1176 152 "clk" "" } { 136 936 960 152 "clk" "" } { 376 2280 2304 392 "clk" "" } { 376 2544 2568 392 "clk" "" } { 368 2000 2024 384 "clk" "" } { 360 1688 1712 376 "clk" "" } { 360 1440 1464 376 "clk" "" } { 360 1152 1176 376 "clk" "" } { 360 864 896 376 "clk" "" } { 360 608 640 376 "clk" "" } { 756 360 376 784 "clk" "" } { 752 696 712 784 "clk" "" } { 752 968 984 784 "clk" "" } { 744 1256 1272 776 "clk" "" } { 760 1792 1808 792 "clk" "" } { 752 2064 2080 784 "clk" "" } { 760 2320 2336 800 "clk" "" } { 1024 416 440 1040 "clk" "" } { 1016 1016 1032 1032 "clk" "" } { 744 1496 1512 784 "clk" "" } { 1032 1536 1552 1048 "clk" "" } { 1224 656 688 1240 "clk" "" } { 1192 1784 1808 1208 "clk" "" } { 1292 1336 1352 1320 "clk" "" } { 1032 2128 2152 1048 "clk" "" } { 616 904 928 632 "clk" "" } { 600 1168 1190 616 "clk" "" } { 600 1424 1456 616 "clk" "" } { 616 1728 1750 632 "clk" "" } { 616 1968 1992 632 "clk" "" } { 648 2240 2264 664 "clk" "" } { 616 2488 2520 632 "clk" "" } { 144 1840 1872 160 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clear Global clock in PIN 66 " "Info: Automatically promoted signal \"clear\" to use Global clock in PIN 66" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 160 408 576 176 "clear" "" } { 160 2056 2089 176 "clear" "" } { 168 2288 2322 184 "clear" "" } { 160 1848 1876 176 "clear" "" } { 160 1616 1648 176 "clear" "" } { 160 1392 1426 176 "clear" "" } { 152 1144 1176 168 "clear" "" } { 152 936 967 168 "clear" "" } { 632 904 935 648 "clear" "" } { 616 1168 1199 632 "clear" "" } { 616 1424 1456 632 "clear" "" } { 640 1728 1751 652 "clear" "" } { 632 1968 1999 648 "clear" "" } { 664 2240 2271 680 "clear" "" } { 632 2488 2520 648 "clear" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}