add9910.vhd

来自「我自己用VHDL语言编的16阶FIR数字滤波器」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
ENTITY add9910 is
PORT(clk : in STD_LOGIC;
     Din1,Din2 :in signed (8 downto 0);
     Dout:out signed(9 downto 0));
END add9910;
ARCHITECTURE a of add9910 is
SIGNAL s1: signed(9 downto 0);
SIGNAL s2: signed(9 downto 0);
BEGIN
    s1<=(Din1(8)&Din1);
    s2<=(Din2(8)&Din2);
PROCESS(Din1,Din2,clk)
BEGIN
if clk'event and clk='1' then
Dout<=s1+s2;
end if;
end process;
end a;