mult25.vhd

来自「我自己用VHDL语言编的16阶FIR数字滤波器」· VHDL 代码 · 共 37 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult25 is
PORT
( clk :  IN STD_LOGIC;
  Din :  IN SIGNED (9 DOWNTO 0);
 Dout :  OUT SIGNED (13 DOWNTO 0));
END mult25;
--16+8+4+1
ARCHITECTURE a OF mult25 IS
SIGNAL s1 : SIGNED (13 DOWNTO 0);
SIGNAL s2 : SIGNED (12 DOWNTO 0);
SIGNAL s3 : SIGNED (13 DOWNTO 0);

BEGIN
P1:process(Din)
BEGIN
s1(13 DOWNTO 4)<=Din;
s1( 3 DOWNTO 0)<="0000";
s2(12 DOWNTO 3)<=Din;
s2(2  DOWNTO 0)<="000";
if Din(9)='0' then 
s3<=('0'&s1(13 downto 1))+("00"&s2(12 DOWNTO 1))+("00000"&Din(9 DOWNTO 1));

else 
s3<=('1'&s1(13 downto 1))+("11"&s2(12 DOWNTO 1))+("11111"&Din(9 DOWNTO 1));

end if;
end process;
P2: PROCESS(clk)
BEGIN
if clk'event and clk='1' then
Dout<=s3;
end if;
END PROCESS;
END a;