mult3.vhd

来自「我自己用VHDL语言编的16阶FIR数字滤波器」· VHDL 代码 · 共 33 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult3 is
PORT
( clk :  IN STD_LOGIC;
  Din :  IN SIGNED (9 DOWNTO 0);
 Dout :  OUT SIGNED (10 DOWNTO 0));
END mult3;
ARCHITECTURE a OF mult3 IS
SIGNAL s1 : SIGNED (10 DOWNTO 0);
SIGNAL s2 : SIGNED (10 DOWNTO 0);

BEGIN
P1:process(Din)
BEGIN
s1(10 DOWNTO 1)<=Din;
s1(0)<='0';
if Din(9)='0' then 
s2<=('0'&s1(10 downto 1))+("00"&Din(9 DOWNTO 1));

else 
s2<=('1'&s1(10 downto 1))+("11"&Din(9 DOWNTO 1));

end if;
end process;
P2: PROCESS(clk)
BEGIN
if clk'event and clk='1' then
Dout<=s2;
end if;
END PROCESS;
END a;