add151710.vhd

我自己用VHDL语言编的16阶FIR数字滤波器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
ENTITY add151710 is
PORT(clk : in STD_LOGIC;
     Din1:in signed (14 downto 0);
     Din2:in signed (16 downto 0); 
     Dout:out signed(9 downto 0));
END add151710;
ARCHITECTURE a of add151710 is
SIGNAL s1: signed(9 downto 0);
SIGNAL s2: signed(9 downto 0);
BEGIN
    s1<=(Din1(13)&Din1(13)&Din1(14 downto 7));
    s2<=(Din2(16 downto 7));
PROCESS(Din1,Din2,clk)
BEGIN
if clk'event and clk='1' then
Dout<=s1+s2;
end if;
end process;
end a;