fir.qsf

我自己用VHDL语言编的16阶FIR数字滤波器

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		fir_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T100C6
set_global_assignment -name TOP_LEVEL_ENTITY fir
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:15:24  MAY 02, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION OFF -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_timing_analysis
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name VHDL_FILE add111414.vhd
set_global_assignment -name VHDL_FILE add121414.vhd
set_global_assignment -name VHDL_FILE add141415.vhd
set_global_assignment -name VHDL_FILE add141710.vhd
set_global_assignment -name VHDL_FILE add151415.vhd
set_global_assignment -name VHDL_FILE add161717.vhd
set_global_assignment -name VHDL_FILE add9910.vhd
set_global_assignment -name VHDL_FILE dff9.vhd
set_global_assignment -name VHDL_FILE mult19.vhd
set_global_assignment -name VHDL_FILE mult212.vhd
set_global_assignment -name VHDL_FILE mult25.vhd
set_global_assignment -name VHDL_FILE mult29.vhd
set_global_assignment -name VHDL_FILE mult3.vhd
set_global_assignment -name VHDL_FILE mult45.vhd
set_global_assignment -name VHDL_FILE mult6.vhd
set_global_assignment -name VHDL_FILE mult92.vhd
set_global_assignment -name VHDL_FILE sub121414.vhd
set_global_assignment -name VHDL_FILE sub171517.vhd
set_global_assignment -name BDF_FILE fir.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE fir.vwf