异步复位、同步置数的四位二进制计数器.txt

来自「异步复位、同步置数的四位二进制计数器的VHDL源文件」· 文本 代码 · 共 24 行

Library       ieee ;
Use     ieee.std_logic_1164.all ;
Use     ieee.std_logic_unsigned.all ;
Entity     cnt4      is      port 
                   (  clk , rst , en , load :  in    std_logic ;
                       data :  in    std_logic_vector ( 3    downto   0 ) ;
                       cnt :  buffer    std_logic_vector ( 3   downto   0 ) ) ;
End     cnt4 ;
Architecture      archcnt4      of      cnt4      is
Begin
         count : process (rst , clk )
                      begin
                           if      rst = ‘1’     then
                                   cnt <= (others => ‘0’) ;
                           elsif    ( clk’event    AND     clk= ‘1’ )     then
                                        if      lode = ‘1’     then
                                                cnt <= data ;
                                        elsif      en = ‘1’      then
                                                cnt <= cnt + 1 ;
                                       end  if ;
                           end    if ;
               end     process    count ;
End     archcnt4 ;