带使能､异步复位端的十二进制计数器的设计.txt

带使能&#65380 异步复位端的十二进制计数器的 设计的一个例子

Library      ieee ;
Use     ieee.std_logic_1164.all ;
Use     ieee.std_logic_unsigned.all ;
Entity     count12en       is       port (  clk , clr , en : in  std_logic ;
                                                          qa ,qb ,qc ,qd : out   std_logic ) ;
End     count12en ;
Architecture     rtl     of     count12en      is
       signal     count_4 :  std_logic_vector ( 3    downto    0 ) ;
Begin  
             qa <= count_4 (0) ;
             qb <= count_4 (1) ;
             qc <= count_4 (2) ;
             qd <= count_4 (3) ;  ------并行赋值语句
   process ( clk , clr )
   begin
               if     ( clr = ‘1’ )     then
                    count_4 <= “0000” ;
               elsif      ( clk’event     AND     clk = ‘1’  )     then

If     ( en = ‘1’ )       then
                                if     ( count_4 = “1011 ” )     then
                                         count_4 <= “0000 ” ;
                                elsif   ( count_4 <  “1011”  )      then
                                         count_4  <=  count_4 + ‘1’ ;
                                end     if ;
                        end    if ;
               end  if ;
 end      process ;
End  rtl;