count60.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count60 is
  port(  cp:in std_logic;
        en3:in std_logic;
       times:out integer range 0 to 59;
       full:out std_logic
       );
end count60;
 architecture c60 of count60 is
  signal time:integer range 0 to 59;
   begin 
    process(cp,en3)
     begin
      if(en3='0')then time<=0;full<='0'; 
       elsif rising_edge(cp) then 
        if 
           time=59 then time<=0;
           full<='1';
        else 
           time<=time+1;
           full<='0';
       end if;
      end if;
     end process;
     times<=time;
end;