counter.rpt

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-- Equation name is '_LC4_A5', type is buried 
_LC4_A5  = LCELL( _EQ024);
  _EQ024 = !A11 &  _LC1_A5
         # !A11 &  _LC3_A5
         #  A11 &  _LC7_A6;

-- Node name is ':473' 
-- Equation name is '_LC3_A6', type is buried 
_LC3_A6  = LCELL( _EQ025);
  _EQ025 =  A51 &  _LC4_A1 &  var2
         #  A51 & !_LC4_A1 & !var2;

-- Node name is '~485~1' 
-- Equation name is '~485~1', location is LC7_A1, type is buried.
-- synthesized logic cell 
_LC7_A1  = LCELL( _EQ026);
  _EQ026 =  current_state &  en2;

-- Node name is '~485~2' 
-- Equation name is '~485~2', location is LC6_A1, type is buried.
-- synthesized logic cell 
_LC6_A1  = LCELL( _EQ027);
  _EQ027 =  A51 &  _LC7_A1 & !var0 &  var1
         #  A51 &  _LC7_A1 &  var0 & !var1;

-- Node name is ':502' 
-- Equation name is '_LC1_A11', type is buried 
_LC1_A11 = LCELL( _EQ028);
  _EQ028 =  A11 & !var0
         # !A11 &  A21 &  var0
         # !A11 & !A51 &  var0
         # !A21 &  A51 & !var0;

-- Node name is ':542' 
-- Equation name is '_LC2_A5', type is buried 
_LC2_A5  = LCELL( _EQ029);
  _EQ029 =  en2 &  _LC4_A5
         # !en2 &  var3;

-- Node name is ':560' 
-- Equation name is '_LC3_A11', type is buried 
_LC3_A11 = LCELL( _EQ030);
  _EQ030 =  en2 &  _LC1_A11
         # !en2 &  var0;

-- Node name is '~580~1' 
-- Equation name is '~580~1', location is LC1_A1, type is buried.
-- synthesized logic cell 
_LC1_A1  = LCELL( _EQ031);
  _EQ031 = !A21 & !current_state &  _LC2_A4
         # !current_state & !en2;

-- Node name is ':581' 
-- Equation name is '_LC8_A5', type is buried 
_LC8_A5  = LCELL( _EQ032);
  _EQ032 =  current_state &  en2 &  _LC7_A5
         #  current_state & !en2 &  _LC5_A5;

-- Node name is '~604~1' 
-- Equation name is '~604~1', location is LC5_A1, type is buried.
-- synthesized logic cell 
_LC5_A1  = LCELL( _EQ033);
  _EQ033 = !en2 &  var3
         # !A21 &  _LC2_A4 &  var3;

-- Node name is '~652~1' 
-- Equation name is '~652~1', location is LC2_A6, type is buried.
-- synthesized logic cell 
_LC2_A6  = LCELL( _EQ034);
  _EQ034 = !A11 &  _LC5_A6
         #  A11 & !_LC4_A1 &  var2
         #  A11 &  _LC4_A1 & !var2;

-- Node name is '~652~2' 
-- Equation name is '~652~2', location is LC6_A2, type is buried.
-- synthesized logic cell 
_LC6_A2  = LCELL( _EQ035);
  _EQ035 =  current_state &  en2 &  _LC2_A6
         # !en2 &  _LC2_A2;

-- Node name is '~652~3' 
-- Equation name is '~652~3', location is LC8_A2, type is buried.
-- synthesized logic cell 
_LC8_A2  = LCELL( _EQ036);
  _EQ036 =  _LC1_A2 &  _LC2_A2
         #  _LC2_A2 &  _LC4_A2
         #  A51 &  _LC1_A2
         #  A51 &  _LC4_A2;

-- Node name is '~658~1' 
-- Equation name is '~658~1', location is LC7_A9, type is buried.
-- synthesized logic cell 
_LC7_A9  = LCELL( _EQ037);
  _EQ037 =  A21
         #  _LC6_A1
         # !A51 &  _LC1_A9;

-- Node name is '~658~2' 
-- Equation name is '~658~2', location is LC8_A9, type is buried.
-- synthesized logic cell 
_LC8_A9  = LCELL( _EQ038);
  _EQ038 =  current_state &  en2 &  _LC5_A9
         # !en2 &  _LC1_A9;

-- Node name is '~664~1' 
-- Equation name is '~664~1', location is LC7_A11, type is buried.
-- synthesized logic cell 
_LC7_A11 = LCELL( _EQ039);
  _EQ039 = !A11 &  _LC1_A4 & !var0
         # !current_state &  _LC1_A4
         #  A11 & !current_state;

-- Node name is '~664~2' 
-- Equation name is '~664~2', location is LC8_A11, type is buried.
-- synthesized logic cell 
_LC8_A11 = LCELL( _EQ040);
  _EQ040 =  A11 & !var0
         # !A11 &  A21 &  var0;

-- Node name is '~664~3' 
-- Equation name is '~664~3', location is LC5_A11, type is buried.
-- synthesized logic cell 
_LC5_A11 = LCELL( _EQ041);
  _EQ041 =  en2 &  _LC7_A11
         #  current_state &  en2 &  _LC8_A11;

-- Node name is '~664~4' 
-- Equation name is '~664~4', location is LC5_A2, type is buried.
-- synthesized logic cell 
_LC5_A2  = LCELL( _EQ042);
  _EQ042 = !A21 & !current_state
         # !A21 &  _LC2_A4
         # !en2;

-- Node name is '~676~1' 
-- Equation name is '~676~1', location is LC5_A6, type is buried.
-- synthesized logic cell 
_LC5_A6  = LCELL( _EQ043);
  _EQ043 = !A21 &  _LC3_A6
         #  A21 & !var1 &  var2
         #  A21 &  var1 & !var2;

-- Node name is '~676~2' 
-- Equation name is '~676~2', location is LC6_A6, type is buried.
-- synthesized logic cell 
_LC6_A6  = LCELL( _EQ044);
  _EQ044 = !A11 &  _LC5_A6
         #  A11 & !_LC4_A1 &  var2
         #  A11 &  _LC4_A1 & !var2;

-- Node name is '~676~3' 
-- Equation name is '~676~3', location is LC8_A6, type is buried.
-- synthesized logic cell 
_LC8_A6  = LCELL( _EQ045);
  _EQ045 =  current_state &  en2 &  _LC6_A6
         # !en2 &  var2;

-- Node name is '~676~4' 
-- Equation name is '~676~4', location is LC7_A2, type is buried.
-- synthesized logic cell 
_LC7_A2  = LCELL( _EQ046);
  _EQ046 =  A51 &  _LC1_A2
         #  A51 &  _LC4_A2
         #  _LC1_A2 &  var2
         #  _LC4_A2 &  var2;

-- Node name is '~682~1' 
-- Equation name is '~682~1', location is LC2_A9, type is buried.
-- synthesized logic cell 
_LC2_A9  = LCELL( _EQ047);
  _EQ047 = !A11 & !A21 &  current_state
         # !A11 & !current_state &  en2;

-- Node name is '~682~2' 
-- Equation name is '~682~2', location is LC3_A9, type is buried.
-- synthesized logic cell 
_LC3_A9  = LCELL( _EQ048);
  _EQ048 =  A21
         #  _LC6_A1
         # !A51 &  var1;

-- Node name is '~682~3' 
-- Equation name is '~682~3', location is LC5_A9, type is buried.
-- synthesized logic cell 
_LC5_A9  = LCELL( _EQ049);
  _EQ049 = !A11 &  A21 & !var1
         #  A11 & !var0 &  var1
         #  A11 &  var0 & !var1;

-- Node name is '~682~4' 
-- Equation name is '~682~4', location is LC6_A9, type is buried.
-- synthesized logic cell 
_LC6_A9  = LCELL( _EQ050);
  _EQ050 =  current_state &  en2 &  _LC5_A9
         # !en2 &  var1;



Project Information                                       d:\vhdl3\counter.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,606K