📄 counter.rpt
字号:
- 4 - A 06 OR2 0 3 0 2 |LPM_ADD_SUB:384|addcore:adder|:77
- 2 - A 04 AND2 s 2 0 0 5 reset~1
- 1 - A 04 AND2 s 2 0 0 1 reset~2
- 5 - A 05 DFFE + 1 2 1 2 :7
- 2 - A 02 DFFE + 1 2 1 2 :9
- 1 - A 09 DFFE + 1 3 1 2 :11
- 3 - A 02 DFFE + 1 2 1 0 :13
- 3 - A 01 DFFE + 1 1 0 15 current_state (:15)
- 2 - A 01 DFFE + 1 3 0 6 var3 (:18)
- 4 - A 02 AND2 s 1 2 0 2 var2~1 (~19~1)
- 1 - A 06 DFFE + 1 2 0 9 var2 (:19)
- 4 - A 09 DFFE + 1 3 0 7 var1 (:20)
- 2 - A 11 DFFE + 1 3 0 9 var0 (:21)
- 4 - A 11 OR2 2 1 0 1 :240
- 8 - A 01 OR2 s ! 2 1 0 1 ~285~1
- 6 - A 11 OR2 2 2 0 1 :303
- 6 - A 05 OR2 2 2 0 1 :414
- 7 - A 05 OR2 1 3 0 1 :418
- 3 - A 05 OR2 1 3 0 2 :464
- 1 - A 05 OR2 2 2 0 1 :465
- 4 - A 05 OR2 1 3 0 1 :466
- 3 - A 06 OR2 1 2 0 1 :473
- 7 - A 01 AND2 s 1 1 0 1 ~485~1
- 6 - A 01 OR2 s 1 3 0 2 ~485~2
- 1 - A 11 OR2 3 1 0 1 :502
- 2 - A 05 OR2 1 2 0 1 :542
- 3 - A 11 OR2 1 2 0 1 :560
- 1 - A 01 OR2 s 2 2 0 1 ~580~1
- 8 - A 05 OR2 1 3 0 1 :581
- 5 - A 01 OR2 s 2 2 0 1 ~604~1
- 2 - A 06 OR2 s 1 3 0 1 ~652~1
- 6 - A 02 OR2 s 1 3 0 1 ~652~2
- 8 - A 02 OR2 s 1 3 0 1 ~652~3
- 7 - A 09 OR2 s 2 2 0 1 ~658~1
- 8 - A 09 OR2 s 1 3 0 1 ~658~2
- 7 - A 11 OR2 s 1 3 0 1 ~664~1
- 8 - A 11 OR2 s 2 1 0 1 ~664~2
- 5 - A 11 OR2 s 1 3 0 1 ~664~3
- 5 - A 02 OR2 s 2 2 0 1 ~664~4
- 5 - A 06 OR2 s 1 3 0 2 ~676~1
- 6 - A 06 OR2 s 1 3 0 1 ~676~2
- 8 - A 06 OR2 s 1 3 0 1 ~676~3
- 7 - A 02 OR2 s 1 3 0 1 ~676~4
- 2 - A 09 OR2 s 3 1 0 2 ~682~1
- 3 - A 09 OR2 s 2 2 0 1 ~682~2
- 5 - A 09 OR2 s 2 2 0 2 ~682~3
- 6 - A 09 OR2 s 1 3 0 1 ~682~4
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\vhdl3\counter.rpt
counter
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 16/ 96( 16%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl3\counter.rpt
counter
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 cp
Device-Specific Information: d:\vhdl3\counter.rpt
counter
** EQUATIONS **
A11 : INPUT;
A21 : INPUT;
A51 : INPUT;
cp : INPUT;
en2 : INPUT;
reset : INPUT;
-- Node name is 'A51~1'
-- Equation name is 'A51~1', location is LC1_A2, type is buried.
-- synthesized logic cell
_LC1_A2 = LCELL( _EQ001);
_EQ001 = !A11 & !A21 & !current_state & en2;
-- Node name is 'b0'
-- Equation name is 'b0', type is output
b0 = _LC3_A2;
-- Node name is 'b1'
-- Equation name is 'b1', type is output
b1 = _LC1_A9;
-- Node name is 'b2'
-- Equation name is 'b2', type is output
b2 = _LC2_A2;
-- Node name is 'b3'
-- Equation name is 'b3', type is output
b3 = _LC5_A5;
-- Node name is ':15' = 'current_state'
-- Equation name is 'current_state', location is LC3_A1, type is buried.
current_state = DFFE( _EQ002, GLOBAL( cp), VCC, VCC, VCC);
_EQ002 = current_state & !reset
# !_LC8_A1 & !reset;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC2_A4, type is buried.
-- synthesized logic cell
_LC2_A4 = LCELL( _EQ003);
_EQ003 = !A11 & !A51;
-- Node name is 'reset~2'
-- Equation name is 'reset~2', location is LC1_A4, type is buried.
-- synthesized logic cell
_LC1_A4 = LCELL( _EQ004);
_EQ004 = !A21 & A51;
-- Node name is ':21' = 'var0'
-- Equation name is 'var0', location is LC2_A11, type is buried.
var0 = DFFE( _EQ005, GLOBAL( cp), VCC, VCC, VCC);
_EQ005 = current_state & _LC3_A11 & !reset
# !current_state & _LC6_A11 & !reset;
-- Node name is ':20' = 'var1'
-- Equation name is 'var1', location is LC4_A9, type is buried.
var1 = DFFE( _EQ006, GLOBAL( cp), VCC, VCC, VCC);
_EQ006 = _LC2_A9 & _LC3_A9 & !reset
# _LC6_A9 & !reset;
-- Node name is '~19~1' = 'var2~1'
-- Equation name is '~19~1', location is LC4_A2, type is buried.
-- synthesized logic cell
_LC4_A2 = LCELL( _EQ007);
_EQ007 = !A21 & current_state & _LC2_A4;
-- Node name is ':19' = 'var2'
-- Equation name is 'var2', location is LC1_A6, type is buried.
var2 = DFFE( _EQ008, GLOBAL( cp), VCC, VCC, VCC);
_EQ008 = _LC8_A6 & !reset
# _LC7_A2 & !reset;
-- Node name is ':18' = 'var3'
-- Equation name is 'var3', location is LC2_A1, type is buried.
var3 = DFFE( _EQ009, GLOBAL( cp), VCC, VCC, VCC);
_EQ009 = current_state & _LC2_A5 & !reset
# !current_state & _LC5_A1 & !reset;
-- Node name is '|LPM_ADD_SUB:340|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = LCELL( _EQ010);
_EQ010 = var0 & var1;
-- Node name is '|LPM_ADD_SUB:340|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_A6', type is buried
_LC7_A6 = LCELL( _EQ011);
_EQ011 = !var2 & var3
# !_LC4_A1 & var3
# _LC4_A1 & var2 & !var3;
-- Node name is '|LPM_ADD_SUB:384|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = LCELL( _EQ012);
_EQ012 = !_LC4_A1 & !var2 & var3
# var2 & !var3
# _LC4_A1 & !var3;
-- Node name is ':7'
-- Equation name is '_LC5_A5', type is buried
_LC5_A5 = DFFE( _EQ013, GLOBAL( cp), VCC, VCC, VCC);
_EQ013 = _LC8_A5 & !reset
# _LC1_A1 & _LC5_A5 & !reset;
-- Node name is ':9'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = DFFE( _EQ014, GLOBAL( cp), VCC, VCC, VCC);
_EQ014 = _LC6_A2 & !reset
# _LC8_A2 & !reset;
-- Node name is ':11'
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = DFFE( _EQ015, GLOBAL( cp), VCC, VCC, VCC);
_EQ015 = _LC2_A9 & _LC7_A9 & !reset
# _LC8_A9 & !reset;
-- Node name is ':13'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = DFFE( _EQ016, GLOBAL( cp), VCC, VCC, VCC);
_EQ016 = _LC5_A11 & !reset
# _LC3_A2 & _LC5_A2 & !reset;
-- Node name is ':240'
-- Equation name is '_LC4_A11', type is buried
_LC4_A11 = LCELL( _EQ017);
_EQ017 = !A21 & A51
# !A21 & var0;
-- Node name is '~285~1'
-- Equation name is '~285~1', location is LC8_A1, type is buried.
-- synthesized logic cell
!_LC8_A1 = _LC8_A1~NOT;
_LC8_A1~NOT = LCELL( _EQ018);
_EQ018 = A21 & en2
# en2 & !_LC2_A4;
-- Node name is ':303'
-- Equation name is '_LC6_A11', type is buried
_LC6_A11 = LCELL( _EQ019);
_EQ019 = !en2 & var0
# A11 & en2
# en2 & _LC4_A11;
-- Node name is ':414'
-- Equation name is '_LC6_A5', type is buried
_LC6_A5 = LCELL( _EQ020);
_EQ020 = !A21 & A51 & _LC4_A6
# !A21 & !A51 & _LC5_A5;
-- Node name is ':418'
-- Equation name is '_LC7_A5', type is buried
_LC7_A5 = LCELL( _EQ021);
_EQ021 = A11 & _LC7_A6
# !A11 & _LC6_A5
# !A11 & _LC3_A5;
-- Node name is ':464'
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = LCELL( _EQ022);
_EQ022 = A21 & !var2 & var3
# A21 & !var1 & var3
# A21 & var1 & var2 & !var3;
-- Node name is ':465'
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = LCELL( _EQ023);
_EQ023 = !A21 & A51 & _LC4_A6
# !A21 & !A51 & var3;
-- Node name is ':466'
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