control.rpt

自动售货机 带选择商品,找零,退币,无货提示,单价显示,选择数量等空能

_LC8_B17 = LCELL( _EQ024);
  _EQ024 =  _LC7_B17
         #  _LC1_B19;

-- Node name is ':328' 
-- Equation name is '_LC4_B17', type is buried 
_LC4_B17 = LCELL( _EQ025);
  _EQ025 =  _LC2_B17 & !start;

-- Node name is ':414' 
-- Equation name is '_LC1_B14', type is buried 
_LC1_B14 = LCELL( _EQ026);
  _EQ026 = !b0 & !b1 & !b2 & !b3;

-- Node name is ':473' 
-- Equation name is '_LC8_B19', type is buried 
!_LC8_B19 = _LC8_B19~NOT;
_LC8_B19~NOT = LCELL( _EQ027);
  _EQ027 =  b3 & !var3
         #  b3 & !_LC2_B19
         # !_LC2_B19 & !var3;

-- Node name is ':477' 
-- Equation name is '_LC2_B23', type is buried 
!_LC2_B23 = _LC2_B23~NOT;
_LC2_B23~NOT = LCELL( _EQ028);
  _EQ028 =  b3 & !var3
         # !b3 &  var3;

-- Node name is ':478' 
-- Equation name is '_LC2_B19', type is buried 
!_LC2_B19 = _LC2_B19~NOT;
_LC2_B19~NOT = LCELL( _EQ029);
  _EQ029 =  b2 & !var2
         #  b2 & !_LC8_B22
         # !_LC8_B22 & !var2;

-- Node name is ':483' 
-- Equation name is '_LC8_B22', type is buried 
!_LC8_B22 = _LC8_B22~NOT;
_LC8_B22~NOT = LCELL( _EQ030);
  _EQ030 =  b1 & !var1
         #  b0 &  b1
         #  b0 & !var1
         #  b1 & !var0
         # !var0 & !var1;

-- Node name is ':490' 
-- Equation name is '_LC2_B14', type is buried 
!_LC2_B14 = _LC2_B14~NOT;
_LC2_B14~NOT = LCELL( _EQ031);
  _EQ031 = !_LC8_B19
         # !T;

-- Node name is ':602' 
-- Equation name is '_LC5_B23', type is buried 
_LC5_B23 = LCELL( _EQ032);
  _EQ032 =  b3 &  _LC2_B14
         #  _LC1_B23 & !_LC2_B14 & !start;

-- Node name is ':608' 
-- Equation name is '_LC6_B23', type is buried 
_LC6_B23 = LCELL( _EQ033);
  _EQ033 =  _LC4_B23 & !_LC8_B19 & !T
         #  _LC5_B23 &  _LC8_B19
         #  _LC5_B23 &  T;

-- Node name is ':621' 
-- Equation name is '_LC7_B23', type is buried 
_LC7_B23 = LCELL( _EQ034);
  _EQ034 =  _LC1_B14 &  _LC1_B23 & !start;

-- Node name is ':626' 
-- Equation name is '_LC4_B14', type is buried 
_LC4_B14 = LCELL( _EQ035);
  _EQ035 =  b2 &  _LC2_B14
         # !_LC2_B14 &  _LC6_B14 & !start;

-- Node name is ':629' 
-- Equation name is '_LC5_B14', type is buried 
_LC5_B14 = LCELL( _EQ036);
  _EQ036 =  _LC3_B14 & !_LC8_B19 & !T
         #  _LC4_B14 &  _LC8_B19
         #  _LC4_B14 &  T;

-- Node name is ':636' 
-- Equation name is '_LC7_B14', type is buried 
_LC7_B14 = LCELL( _EQ037);
  _EQ037 =  _LC1_B14 &  _LC6_B14 & !start;

-- Node name is ':641' 
-- Equation name is '_LC2_B22', type is buried 
_LC2_B22 = LCELL( _EQ038);
  _EQ038 =  b1 &  _LC2_B14
         #  _LC1_B22 & !_LC2_B14 & !start;

-- Node name is ':644' 
-- Equation name is '_LC5_B22', type is buried 
_LC5_B22 = LCELL( _EQ039);
  _EQ039 =  _LC2_B22 &  _LC8_B19
         #  _LC2_B22 &  T
         #  _LC4_B22 & !_LC8_B19 & !T;

-- Node name is ':651' 
-- Equation name is '_LC6_B22', type is buried 
_LC6_B22 = LCELL( _EQ040);
  _EQ040 =  _LC1_B14 &  _LC1_B22 & !start;

-- Node name is ':656' 
-- Equation name is '_LC1_B15', type is buried 
_LC1_B15 = LCELL( _EQ041);
  _EQ041 =  b0 &  _LC2_B14
         # !_LC2_B14 &  _LC5_B15 & !start;

-- Node name is ':659' 
-- Equation name is '_LC3_B15', type is buried 
_LC3_B15 = LCELL( _EQ042);
  _EQ042 =  _LC1_B15 &  _LC8_B19
         #  _LC1_B15 &  T
         #  _LC2_B15;

-- Node name is ':660' 
-- Equation name is '_LC2_B15', type is buried 
_LC2_B15 = LCELL( _EQ043);
  _EQ043 =  b0 & !_LC8_B19 & !T & !var0
         # !b0 & !_LC8_B19 & !T &  var0;

-- Node name is ':666' 
-- Equation name is '_LC4_B15', type is buried 
_LC4_B15 = LCELL( _EQ044);
  _EQ044 =  _LC1_B14 &  _LC5_B15 & !start;

-- Node name is '~667~1' 
-- Equation name is '~667~1', location is LC3_B23, type is buried.
-- synthesized logic cell 
_LC3_B23 = LCELL( _EQ045);
  _EQ045 = !_LC1_B14 & !_LC8_B19
         # !_LC1_B14 &  T;

-- Node name is ':709' 
-- Equation name is '_LC3_B20', type is buried 
_LC3_B20 = LCELL( _EQ046);
  _EQ046 =  _LC8_B19 & !T
         # !_LC8_B19 &  T;

-- Node name is ':710' 
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = LCELL( _EQ047);
  _EQ047 =  _LC8_B19 & !T
         #  _LC1_B14
         #  _LC3_B20;

-- Node name is ':725' 
-- Equation name is '_LC1_B17', type is buried 
!_LC1_B17 = _LC1_B17~NOT;
_LC1_B17~NOT = LCELL( _EQ048);
  _EQ048 = !_LC1_B14 &  _LC8_B19 &  T;

-- Node name is ':798' 
-- Equation name is '_LC8_B23', type is buried 
_LC8_B23 = LCELL( _EQ049);
  _EQ049 =  current_state &  _LC3_B23 &  _LC6_B23
         #  current_state &  _LC7_B23;

-- Node name is ':804' 
-- Equation name is '_LC8_B14', type is buried 
_LC8_B14 = LCELL( _EQ050);
  _EQ050 =  current_state &  _LC3_B23 &  _LC5_B14
         #  current_state &  _LC7_B14;

-- Node name is ':810' 
-- Equation name is '_LC7_B22', type is buried 
_LC7_B22 = LCELL( _EQ051);
  _EQ051 =  current_state &  _LC3_B23 &  _LC5_B22
         #  current_state &  _LC6_B22;

-- Node name is ':816' 
-- Equation name is '_LC7_B15', type is buried 
_LC7_B15 = LCELL( _EQ052);
  _EQ052 =  current_state &  _LC3_B15 &  _LC3_B23
         #  current_state &  _LC4_B15;

-- Node name is ':822' 
-- Equation name is '_LC4_B19', type is buried 
_LC4_B19 = LCELL( _EQ053);
  _EQ053 =  current_state &  _LC3_B19
         #  current_state & !_LC3_B20
         #  current_state & !_LC3_B23;

-- Node name is ':828' 
-- Equation name is '_LC4_B20', type is buried 
_LC4_B20 = LCELL( _EQ054);
  _EQ054 =  _LC2_B20 & !_LC3_B20
         #  _LC2_B20 &  _LC7_B20 & !start;

-- Node name is '~834~1' 
-- Equation name is '~834~1', location is LC2_B20, type is buried.
-- synthesized logic cell 
_LC2_B20 = LCELL( _EQ055);
  _EQ055 =  current_state &  _LC3_B23;

-- Node name is ':834' 
-- Equation name is '_LC8_B20', type is buried 
_LC8_B20 = LCELL( _EQ056);
  _EQ056 =  _LC2_B20 &  _LC6_B20 & !_LC8_B19
         #  _LC2_B20 &  _LC6_B20 & !T
         #  _LC2_B20 & !_LC8_B19 & !T;

-- Node name is '~851~1' 
-- Equation name is '~851~1', location is LC5_B17, type is buried.
-- synthesized logic cell 
_LC5_B17 = LCELL( _EQ057);
  _EQ057 = !current_state & !_LC1_B19 & !start;

-- Node name is '~874~1' 
-- Equation name is '~874~1', location is LC2_B24, type is buried.
-- synthesized logic cell 
_LC2_B24 = LCELL( _EQ058);
  _EQ058 =  current_state
         #  _LC1_B19;



Project Information                                       d:\vhdl3\control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,920K