📄 control.rpt
字号:
- 8 - B 19 OR2 ! 1 2 0 11 :473
- 2 - B 23 OR2 ! 1 1 0 1 :477
- 2 - B 19 OR2 ! 1 2 0 1 :478
- 8 - B 22 OR2 ! 2 2 0 1 :483
- 2 - B 14 OR2 ! 1 1 0 4 :490
- 5 - B 23 OR2 2 2 0 1 :602
- 6 - B 23 OR2 1 3 0 1 :608
- 7 - B 23 AND2 1 2 0 1 :621
- 4 - B 14 OR2 2 2 0 1 :626
- 5 - B 14 OR2 1 3 0 1 :629
- 7 - B 14 AND2 1 2 0 1 :636
- 2 - B 22 OR2 2 2 0 1 :641
- 5 - B 22 OR2 1 3 0 1 :644
- 6 - B 22 AND2 1 2 0 1 :651
- 1 - B 15 OR2 2 2 0 1 :656
- 3 - B 15 OR2 1 3 0 1 :659
- 2 - B 15 OR2 2 2 0 1 :660
- 4 - B 15 AND2 1 2 0 1 :666
- 3 - B 23 OR2 s 1 2 0 6 ~667~1
- 3 - B 20 OR2 1 1 0 3 :709
- 1 - B 20 OR2 1 3 0 1 :710
- 1 - B 17 AND2 ! 1 2 0 3 :725
- 8 - B 23 OR2 0 4 0 1 :798
- 8 - B 14 OR2 0 4 0 1 :804
- 7 - B 22 OR2 0 4 0 1 :810
- 7 - B 15 OR2 0 4 0 1 :816
- 4 - B 19 OR2 0 4 0 1 :822
- 4 - B 20 OR2 1 3 0 1 :828
- 2 - B 20 AND2 s 0 2 0 2 ~834~1
- 8 - B 20 OR2 1 3 0 1 :834
- 5 - B 17 AND2 s 1 2 0 2 ~851~1
- 2 - B 24 OR2 s 0 2 0 10 ~874~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\vhdl3\control.rpt
control
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 19/ 96( 19%) 0/ 48( 0%) 7/ 48( 14%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl3\control.rpt
control
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 cp
Device-Specific Information: d:\vhdl3\control.rpt
control
** EQUATIONS **
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
cp : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
start : INPUT;
T : INPUT;
-- Node name is ':34' = 'current_state'
-- Equation name is 'current_state', location is LC1_B24, type is buried.
current_state = DFFE( _EQ001, GLOBAL( cp), VCC, VCC, VCC);
_EQ001 = current_state & !start
# !_LC2_B24;
-- Node name is 'c0'
-- Equation name is 'c0', type is output
c0 = _LC5_B15;
-- Node name is 'c1'
-- Equation name is 'c1', type is output
c1 = _LC1_B22;
-- Node name is 'c2'
-- Equation name is 'c2', type is output
c2 = _LC6_B14;
-- Node name is 'c3'
-- Equation name is 'c3', type is output
c3 = _LC1_B23;
-- Node name is 'en1'
-- Equation name is 'en1', type is output
en1 = _LC7_B17;
-- Node name is 'en2'
-- Equation name is 'en2', type is output
en2 = _LC6_B17;
-- Node name is 'en3'
-- Equation name is 'en3', type is output
en3 = _LC3_B17;
-- Node name is 'out1'
-- Equation name is 'out1', type is output
out1 = _LC5_B20;
-- Node name is 'reject1'
-- Equation name is 'reject1', type is output
reject1 = _LC7_B19;
-- Node name is 'reject2'
-- Equation name is 'reject2', type is output
reject2 = _LC7_B20;
-- Node name is 'reset'
-- Equation name is 'reset', type is output
reset = _LC2_B17;
-- Node name is ':41' = 'var0'
-- Equation name is 'var0', location is LC6_B15, type is buried.
var0 = DFFE( _EQ002, GLOBAL( cp), VCC, VCC, VCC);
_EQ002 = _LC2_B24 & var0
# !current_state & d0;
-- Node name is ':40' = 'var1'
-- Equation name is 'var1', location is LC3_B22, type is buried.
var1 = DFFE( _EQ003, GLOBAL( cp), VCC, VCC, VCC);
_EQ003 = _LC2_B24 & var1
# !current_state & d1;
-- Node name is ':39' = 'var2'
-- Equation name is 'var2', location is LC6_B19, type is buried.
var2 = DFFE( _EQ004, GLOBAL( cp), VCC, VCC, VCC);
_EQ004 = _LC2_B24 & var2
# !current_state & d2;
-- Node name is ':38' = 'var3'
-- Equation name is 'var3', location is LC5_B19, type is buried.
var3 = DFFE( _EQ005, GLOBAL( cp), VCC, VCC, VCC);
_EQ005 = _LC2_B24 & var3
# !current_state & d3;
-- Node name is '|LPM_ADD_SUB:536|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_B15', type is buried
_LC8_B15 = LCELL( _EQ006);
_EQ006 = b1 & !var1
# b0 & b1
# b0 & !var1
# b1 & !var0
# !var0 & !var1;
-- Node name is '|LPM_ADD_SUB:536|addcore:adder|:79' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC4_B22', type is buried
_LC4_B22 = LCELL( _EQ007);
_EQ007 = !b0 & b1 & var0 & var1
# !b0 & !b1 & var0 & !var1
# b0 & b1 & !var1
# b0 & !b1 & var1
# b1 & !var0 & !var1
# !b1 & !var0 & var1;
-- Node name is '|LPM_ADD_SUB:536|addcore:adder|:80' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = LCELL( _EQ008);
_EQ008 = b2 & _LC8_B15 & !var2
# !b2 & _LC8_B15 & var2
# b2 & !_LC8_B15 & var2
# !b2 & !_LC8_B15 & !var2;
-- Node name is '|LPM_ADD_SUB:536|addcore:adder|:81' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = LCELL( _EQ009);
_EQ009 = !b2 & _LC2_B23 & var2
# !b2 & _LC2_B23 & !_LC8_B15
# _LC2_B23 & !_LC8_B15 & var2
# b2 & !_LC2_B23 & _LC8_B15
# !_LC2_B23 & _LC8_B15 & !var2
# b2 & !_LC2_B23 & !var2;
-- Node name is ':12'
-- Equation name is '_LC7_B17', type is buried
_LC7_B17 = DFFE( _EQ010, GLOBAL( cp), VCC, VCC, VCC);
_EQ010 = !current_state & _LC8_B17
# !current_state & start
# current_state & !_LC1_B17;
-- Node name is ':14'
-- Equation name is '_LC6_B17', type is buried
_LC6_B17 = DFFE( _EQ011, GLOBAL( cp), VCC, VCC, VCC);
_EQ011 = current_state & _LC1_B20
# _LC5_B17 & _LC6_B17;
-- Node name is ':16'
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = DFFE( _EQ012, GLOBAL( cp), VCC, VCC, VCC);
_EQ012 = current_state & _LC1_B17
# _LC3_B17 & _LC5_B17;
-- Node name is ':18'
-- Equation name is '_LC2_B17', type is buried
_LC2_B17 = DFFE( _EQ013, GLOBAL( cp), VCC, VCC, VCC);
_EQ013 = current_state & !_LC1_B17
# !current_state & _LC4_B17
# !current_state & _LC1_B19;
-- Node name is ':20'
-- Equation name is '_LC5_B20', type is buried
_LC5_B20 = DFFE( _EQ014, GLOBAL( cp), VCC, VCC, VCC);
_EQ014 = _LC8_B20
# !current_state & !_LC1_B19 & _LC6_B20;
-- Node name is ':22'
-- Equation name is '_LC7_B19', type is buried
_LC7_B19 = DFFE( _EQ015, GLOBAL( cp), VCC, VCC, VCC);
_EQ015 = _LC4_B19
# !current_state & !_LC1_B19 & _LC3_B19;
-- Node name is ':24'
-- Equation name is '_LC7_B20', type is buried
_LC7_B20 = DFFE( _EQ016, GLOBAL( cp), VCC, VCC, VCC);
_EQ016 = _LC4_B20
# !_LC2_B24 & _LC7_B20 & !start;
-- Node name is ':26'
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = DFFE( _EQ017, GLOBAL( cp), VCC, VCC, VCC);
_EQ017 = _LC8_B23
# _LC1_B23 & !_LC2_B24 & !start;
-- Node name is ':28'
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = DFFE( _EQ018, GLOBAL( cp), VCC, VCC, VCC);
_EQ018 = _LC8_B14
# !_LC2_B24 & _LC6_B14 & !start;
-- Node name is ':30'
-- Equation name is '_LC1_B22', type is buried
_LC1_B22 = DFFE( _EQ019, GLOBAL( cp), VCC, VCC, VCC);
_EQ019 = _LC7_B22
# _LC1_B22 & !_LC2_B24 & !start;
-- Node name is ':32'
-- Equation name is '_LC5_B15', type is buried
_LC5_B15 = DFFE( _EQ020, GLOBAL( cp), VCC, VCC, VCC);
_EQ020 = _LC7_B15
# !_LC2_B24 & _LC5_B15 & !start;
-- Node name is ':173'
-- Equation name is '_LC3_B19', type is buried
_LC3_B19 = LCELL( _EQ021);
_EQ021 = _LC7_B19 & !start;
-- Node name is ':185'
-- Equation name is '_LC6_B20', type is buried
_LC6_B20 = LCELL( _EQ022);
_EQ022 = _LC5_B20 & !start;
-- Node name is ':224'
-- Equation name is '_LC1_B19', type is buried
_LC1_B19 = LCELL( _EQ023);
_EQ023 = !d0 & !d1 & !d2 & !d3;
-- Node name is '~320~1'
-- Equation name is '~320~1', location is LC8_B17, type is buried.
-- synthesized logic cell
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