📄 count60_show.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count60_show is
port(inte:in integer range 0 to 59;
--ten:out std_logic_vector()
a1,b1,c1,d1,e1,f1,g1:out std_logic;
a2,b2,c2,d2,e2,f2,g2:out std_logic
);
end count60_show;
architecture c60_show of count60_show is
begin
process(inte)
type data_out is array(0 to 6) of std_logic;
variable one:data_out;
variable ten:data_out;
begin
case inte is
when 0|10|20|30|40|50=>one:="1111110";
when 1|11|21|31|41|51=>one:="0110000";
when 2|12|22|32|42|52=>one:="1101101";
when 3|13|23|33|43|53=>one:="1111001";
when 4|14|24|34|44|54=>one:="0110011";
when 5|15|25|35|45|55=>one:="1011011";
when 6|16|26|36|46|56=>one:="0011111";
when 7|17|27|37|47|57=>one:="1110000";
when 8|18|28|38|48|58=>one:="1111111";
when 9|19|29|39|49|59=>one:="1110011";
when others =>null;
end case;
case inte is
when 0|1|2|3|4|5|6|7|8|9=>ten:="1111110";
when 10|11|12|13|14|15|16|17|18|19=>ten:="0110000";
when 20|21|22|23|24|25|26|27|28|29=>ten:="1101101";
when 30|31|32|33|34|35|36|37|38|39=>ten:="1111001";
when 40|41|42|43|44|45|46|47|48|49=>ten:="0110011";
when 50|51|52|53|54|55|56|57|58|59=>ten:="1011011";
--when 60|61|62|63|64|65|66|67|68|69=>ten:="0011111";
--when 70|71|72|73|74|75|76|77|78|79=>ten:="1110000";
--when 80|81|82|83|84|85|86|87|88|89=>ten:="1111111";
--when 90|91|92|93|94|95|96|97|98|99=>ten:="1110011";
when others =>null;
end case;
a1<=one(0);
b1<=one(1);
c1<=one(2);
d1<=one(3);
e1<=one(4);
f1<=one(5);
g1<=one(6);
a2<=ten(0);
b2<=ten(1);
c2<=ten(2);
d2<=ten(3);
e2<=ten(4);
f2<=ten(5);
g2<=ten(6);
end process;
end c60_show;
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