📄 control2.rpt
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_LC2_A13 = LCELL( _EQ017);
_EQ017 = _LC8_A13 & !start;
-- Node name is ':235'
-- Equation name is '_LC3_A21', type is buried
!_LC3_A21 = _LC3_A21~NOT;
_LC3_A21~NOT = LCELL( _EQ018);
_EQ018 = d1
# d2
# d0
# d3;
-- Node name is ':421'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = LCELL( _EQ019);
_EQ019 = d3 & _LC3_A17
# !b3 & _LC3_A17
# !b3 & d3;
-- Node name is ':426'
-- Equation name is '_LC3_A17', type is buried
_LC3_A17 = LCELL( _EQ020);
_EQ020 = d2 & _LC4_A17
# !b2 & _LC4_A17
# !b2 & d2;
-- Node name is ':431'
-- Equation name is '_LC4_A17', type is buried
_LC4_A17 = LCELL( _EQ021);
_EQ021 = !b1 & d1
# !b0 & d0 & d1
# !b0 & !b1 & d0;
-- Node name is ':438'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = LCELL( _EQ022);
_EQ022 = _LC1_A23 & !T;
-- Node name is ':691'
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = LCELL( _EQ023);
_EQ023 = b3 & d3 & _LC3_A17
# b3 & !d3 & _LC1_A17
# b3 & d3 & !_LC1_A17
# !b3 & !d3 & !_LC1_A17 & !_LC3_A17;
-- Node name is ':697'
-- Equation name is '_LC6_A17', type is buried
_LC6_A17 = LCELL( _EQ024);
_EQ024 = b2 & !d2 & _LC5_A17
# !b2 & d2 & !_LC1_A23 & _LC5_A17
# b2 & d2 & !_LC5_A17
# !b2 & !d2 & !_LC1_A23 & !_LC5_A17
# b2 & _LC1_A23;
-- Node name is ':703'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = LCELL( _EQ025);
_EQ025 = b1 & d1 & !_LC4_A21
# !b1 & !d1 & !_LC1_A23 & !_LC4_A21
# b1 & !d1 & _LC4_A21
# !b1 & d1 & !_LC1_A23 & _LC4_A21
# b1 & _LC1_A23;
-- Node name is ':770'
-- Equation name is '_LC6_A16', type is buried
_LC6_A16 = LCELL( _EQ026);
_EQ026 = current_state0 & !current_state1;
-- Node name is ':774'
-- Equation name is '_LC8_A20', type is buried
_LC8_A20 = LCELL( _EQ027);
_EQ027 = !_LC2_A21 & _LC6_A16;
-- Node name is ':778'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = LCELL( _EQ028);
_EQ028 = !current_state0 & !current_state1;
-- Node name is ':791'
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = LCELL( _EQ029);
_EQ029 = _LC1_A16 & !_LC3_A21;
-- Node name is ':792'
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = LCELL( _EQ030);
_EQ030 = current_state0 & !current_state1 & _LC2_A21
# current_state0 & current_state1 & !start;
-- Node name is ':797'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = LCELL( _EQ031);
_EQ031 = _LC7_A23 & _LC8_A20 & !start;
-- Node name is ':801'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = LCELL( _EQ032);
_EQ032 = !_LC1_A16 & _LC2_A23 & !_LC6_A16
# !_LC1_A16 & _LC3_A23;
-- Node name is ':806'
-- Equation name is '_LC7_A17', type is buried
_LC7_A17 = LCELL( _EQ033);
_EQ033 = _LC2_A17 & _LC8_A20 & !start;
-- Node name is ':810'
-- Equation name is '_LC8_A17', type is buried
_LC8_A17 = LCELL( _EQ034);
_EQ034 = !_LC1_A16 & !_LC6_A16 & _LC6_A17
# !_LC1_A16 & _LC7_A17;
-- Node name is ':815'
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = LCELL( _EQ035);
_EQ035 = _LC8_A16 & _LC8_A20 & !start;
-- Node name is ':819'
-- Equation name is '_LC7_A16', type is buried
_LC7_A16 = LCELL( _EQ036);
_EQ036 = !_LC1_A16 & _LC1_A21 & !_LC6_A16
# !_LC1_A16 & _LC5_A16;
-- Node name is ':825'
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = LCELL( _EQ037);
_EQ037 = b0 & _LC1_A23 & !_LC6_A16
# b0 & !d0 & !_LC6_A16
# !b0 & d0 & !_LC1_A23 & !_LC6_A16;
-- Node name is ':828'
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = LCELL( _EQ038);
_EQ038 = !_LC1_A16 & _LC2_A24
# !_LC1_A16 & _LC2_A13 & _LC8_A20;
-- Node name is ':837'
-- Equation name is '_LC3_A20', type is buried
_LC3_A20 = LCELL( _EQ039);
_EQ039 = _LC2_A20 & _LC6_A16 & !start
# _LC2_A21 & _LC6_A16;
-- Node name is ':842'
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = LCELL( _EQ040);
_EQ040 = _LC4_A24 & _LC8_A20 & !start;
-- Node name is ':846'
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = LCELL( _EQ041);
_EQ041 = !_LC1_A16 & _LC1_A23 & !_LC6_A16
# !_LC1_A16 & _LC3_A24;
-- Node name is ':851'
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = LCELL( _EQ042);
_EQ042 = _LC1_A24 & _LC8_A20 & !start;
-- Node name is ':855'
-- Equation name is '_LC8_A24', type is buried
_LC8_A24 = LCELL( _EQ043);
_EQ043 = !_LC1_A16 & !_LC1_A23 & !_LC6_A16
# !_LC1_A16 & _LC7_A24;
-- Node name is ':863'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = LCELL( _EQ044);
_EQ044 = _LC1_A16 & _LC6_A13
# _LC1_A16 & start
# _LC1_A16 & _LC3_A21;
-- Node name is ':872'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = LCELL( _EQ045);
_EQ045 = _LC1_A16 & _LC8_A23 & !start
# _LC1_A16 & _LC3_A21;
-- Node name is ':882'
-- Equation name is '_LC6_A20', type is buried
_LC6_A20 = LCELL( _EQ046);
_EQ046 = _LC4_A20 & _LC6_A16 & !start
# _LC2_A21 & _LC6_A16;
-- Node name is ':891'
-- Equation name is '_LC5_A20', type is buried
_LC5_A20 = LCELL( _EQ047);
_EQ047 = _LC1_A20 & _LC6_A16 & !start
# _LC2_A21 & _LC6_A16;
Project Information d:\vhdl3\control2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,449K
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