📄 control2.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 21 OR2 2 0 0 1 |LPM_ADD_SUB:655|addcore:adder|pcarry0
- 5 - A 17 OR2 4 0 0 2 |LPM_ADD_SUB:655|addcore:adder|pcarry1
- 1 - A 17 OR2 2 1 0 1 |LPM_ADD_SUB:655|addcore:adder|pcarry2
- 6 - A 13 DFFE + 1 2 1 1 :12
- 4 - A 20 DFFE + 1 2 1 1 :14
- 1 - A 20 DFFE + 1 2 1 1 :16
- 8 - A 23 DFFE + 1 2 1 1 :18
- 1 - A 24 DFFE + 1 2 1 1 :20
- 2 - A 20 DFFE + 1 2 1 1 :22
- 4 - A 24 DFFE + 1 2 1 1 :24
- 7 - A 23 DFFE + 1 2 1 1 :26
- 2 - A 17 DFFE + 1 2 1 1 :28
- 8 - A 16 DFFE + 1 2 1 1 :30
- 8 - A 13 DFFE + 1 2 1 1 :32
- 4 - A 16 DFFE + 1 2 0 3 current_state1 (:34)
- 3 - A 16 DFFE + 0 2 0 3 current_state0 (:35)
- 2 - A 13 AND2 1 1 0 1 :177
- 3 - A 21 OR2 ! 4 0 0 3 :235
- 1 - A 23 OR2 2 1 0 6 :421
- 3 - A 17 OR2 2 1 0 2 :426
- 4 - A 17 OR2 4 0 0 1 :431
- 2 - A 21 AND2 1 1 0 5 :438
- 2 - A 23 OR2 2 2 0 1 :691
- 6 - A 17 OR2 2 2 0 1 :697
- 1 - A 21 OR2 2 2 0 1 :703
- 6 - A 16 AND2 0 2 0 10 :770
- 8 - A 20 AND2 0 2 0 9 :774
- 1 - A 16 AND2 0 2 0 10 :778
- 4 - A 13 AND2 0 2 0 10 :791
- 2 - A 16 OR2 1 3 0 1 :792
- 3 - A 23 AND2 1 2 0 1 :797
- 4 - A 23 OR2 0 4 0 1 :801
- 7 - A 17 AND2 1 2 0 1 :806
- 8 - A 17 OR2 0 4 0 1 :810
- 5 - A 16 AND2 1 2 0 1 :815
- 7 - A 16 OR2 0 4 0 1 :819
- 2 - A 24 OR2 2 2 0 1 :825
- 5 - A 24 OR2 0 4 0 1 :828
- 3 - A 20 OR2 1 3 0 1 :837
- 3 - A 24 AND2 1 2 0 1 :842
- 6 - A 24 OR2 0 4 0 1 :846
- 7 - A 24 AND2 1 2 0 1 :851
- 8 - A 24 OR2 0 4 0 1 :855
- 1 - A 13 OR2 1 3 0 1 :863
- 5 - A 23 OR2 1 3 0 1 :872
- 6 - A 20 OR2 1 3 0 1 :882
- 5 - A 20 OR2 1 3 0 1 :891
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\vhdl3\control2.rpt
control2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 14/ 96( 14%) 0/ 48( 0%) 12/ 48( 25%) 4/16( 25%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl3\control2.rpt
control2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 cp
Device-Specific Information: d:\vhdl3\control2.rpt
control2
** EQUATIONS **
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
cp : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
start : INPUT;
T : INPUT;
-- Node name is ':35' = 'current_state0'
-- Equation name is 'current_state0', location is LC3_A16, type is buried.
current_state0 = DFFE( _EQ001, GLOBAL( cp), VCC, VCC, VCC);
_EQ001 = _LC2_A16
# _LC4_A13;
-- Node name is ':34' = 'current_state1'
-- Equation name is 'current_state1', location is LC4_A16, type is buried.
current_state1 = DFFE( _EQ002, GLOBAL( cp), VCC, VCC, VCC);
_EQ002 = !_LC1_A16 & _LC8_A20
# current_state1 & !_LC1_A16 & !start;
-- Node name is 'c0'
-- Equation name is 'c0', type is output
c0 = _LC8_A13;
-- Node name is 'c1'
-- Equation name is 'c1', type is output
c1 = _LC8_A16;
-- Node name is 'c2'
-- Equation name is 'c2', type is output
c2 = _LC2_A17;
-- Node name is 'c3'
-- Equation name is 'c3', type is output
c3 = _LC7_A23;
-- Node name is 'en1'
-- Equation name is 'en1', type is output
en1 = _LC6_A13;
-- Node name is 'en2'
-- Equation name is 'en2', type is output
en2 = _LC4_A20;
-- Node name is 'en3'
-- Equation name is 'en3', type is output
en3 = _LC1_A20;
-- Node name is 'out1'
-- Equation name is 'out1', type is output
out1 = _LC1_A24;
-- Node name is 'reject1'
-- Equation name is 'reject1', type is output
reject1 = _LC2_A20;
-- Node name is 'reject2'
-- Equation name is 'reject2', type is output
reject2 = _LC4_A24;
-- Node name is 'reset'
-- Equation name is 'reset', type is output
reset = _LC8_A23;
-- Node name is '|LPM_ADD_SUB:655|addcore:adder|pcarry0' from file "addcore.tdf" line 308, column 64
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = LCELL( _EQ003);
_EQ003 = b0
# !d0;
-- Node name is '|LPM_ADD_SUB:655|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_A17', type is buried
_LC5_A17 = LCELL( _EQ004);
_EQ004 = b1 & !d1
# b0 & b1
# b0 & !d1
# b1 & !d0
# !d0 & !d1;
-- Node name is '|LPM_ADD_SUB:655|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A17', type is buried
_LC1_A17 = LCELL( _EQ005);
_EQ005 = b2 & _LC5_A17
# !d2 & _LC5_A17
# b2 & !d2;
-- Node name is ':12'
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = DFFE( _EQ006, GLOBAL( cp), VCC, VCC, VCC);
_EQ006 = _LC6_A13 & _LC8_A20
# _LC8_A20 & start
# _LC1_A13;
-- Node name is ':14'
-- Equation name is '_LC4_A20', type is buried
_LC4_A20 = DFFE( _EQ007, GLOBAL( cp), VCC, VCC, VCC);
_EQ007 = _LC6_A20
# _LC4_A13 & _LC4_A20 & !start;
-- Node name is ':16'
-- Equation name is '_LC1_A20', type is buried
_LC1_A20 = DFFE( _EQ008, GLOBAL( cp), VCC, VCC, VCC);
_EQ008 = _LC5_A20
# _LC1_A20 & _LC4_A13 & !start;
-- Node name is ':18'
-- Equation name is '_LC8_A23', type is buried
_LC8_A23 = DFFE( _EQ009, GLOBAL( cp), VCC, VCC, VCC);
_EQ009 = _LC8_A20 & _LC8_A23 & !start
# _LC5_A23;
-- Node name is ':20'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = DFFE( _EQ010, GLOBAL( cp), VCC, VCC, VCC);
_EQ010 = _LC8_A24
# _LC1_A24 & _LC4_A13 & !start;
-- Node name is ':22'
-- Equation name is '_LC2_A20', type is buried
_LC2_A20 = DFFE( _EQ011, GLOBAL( cp), VCC, VCC, VCC);
_EQ011 = _LC3_A20
# _LC2_A20 & _LC4_A13 & !start;
-- Node name is ':24'
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = DFFE( _EQ012, GLOBAL( cp), VCC, VCC, VCC);
_EQ012 = _LC6_A24
# _LC4_A13 & _LC4_A24 & !start;
-- Node name is ':26'
-- Equation name is '_LC7_A23', type is buried
_LC7_A23 = DFFE( _EQ013, GLOBAL( cp), VCC, VCC, VCC);
_EQ013 = _LC4_A23
# _LC4_A13 & _LC7_A23 & !start;
-- Node name is ':28'
-- Equation name is '_LC2_A17', type is buried
_LC2_A17 = DFFE( _EQ014, GLOBAL( cp), VCC, VCC, VCC);
_EQ014 = _LC8_A17
# _LC2_A17 & _LC4_A13 & !start;
-- Node name is ':30'
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = DFFE( _EQ015, GLOBAL( cp), VCC, VCC, VCC);
_EQ015 = _LC7_A16
# _LC4_A13 & _LC8_A16 & !start;
-- Node name is ':32'
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = DFFE( _EQ016, GLOBAL( cp), VCC, VCC, VCC);
_EQ016 = _LC5_A24
# _LC4_A13 & _LC8_A13 & !start;
-- Node name is ':177'
-- Equation name is '_LC2_A13', type is buried
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