📄 count60.rpt
字号:
- 1 - C 16 DFFE + 0 0 1 4 time0 (:16)
- 8 - C 18 OR2 s 0 3 0 2 ~69~1
- 7 - C 18 OR2 ! 0 3 0 5 :69
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\vhdl3\count60.rpt
count60
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 8/ 96( 8%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl3\count60.rpt
count60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 cp
Device-Specific Information: d:\vhdl3\count60.rpt
count60
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 en3
Device-Specific Information: d:\vhdl3\count60.rpt
count60
** EQUATIONS **
cp : INPUT;
en3 : INPUT;
-- Node name is 'full'
-- Equation name is 'full', type is output
full = _LC6_C18;
-- Node name is 'times0'
-- Equation name is 'times0', type is output
times0 = time0;
-- Node name is 'times1'
-- Equation name is 'times1', type is output
times1 = time1;
-- Node name is 'times2'
-- Equation name is 'times2', type is output
times2 = time2;
-- Node name is 'times3'
-- Equation name is 'times3', type is output
times3 = time3;
-- Node name is 'times4'
-- Equation name is 'times4', type is output
times4 = time4;
-- Node name is 'times5'
-- Equation name is 'times5', type is output
times5 = time5;
-- Node name is ':16' = 'time0'
-- Equation name is 'time0', location is LC1_C16, type is buried.
time0 = DFFE(!time0, GLOBAL( cp), GLOBAL( en3), VCC, VCC);
-- Node name is ':15' = 'time1'
-- Equation name is 'time1', location is LC3_C18, type is buried.
time1 = DFFE( _EQ001, GLOBAL( cp), GLOBAL( en3), VCC, VCC);
_EQ001 = !_LC7_C18 & !time0 & time1
# !_LC7_C18 & time0 & !time1;
-- Node name is ':14' = 'time2'
-- Equation name is 'time2', location is LC5_C18, type is buried.
time2 = DFFE( _EQ002, GLOBAL( cp), GLOBAL( en3), VCC, VCC);
_EQ002 = !_LC4_C18 & !_LC7_C18 & time2
# _LC4_C18 & !_LC7_C18 & !time2;
-- Node name is ':13' = 'time3'
-- Equation name is 'time3', location is LC1_C18, type is buried.
time3 = DFFE( _EQ003, GLOBAL( cp), GLOBAL( en3), VCC, VCC);
_EQ003 = !_LC7_C18 & !time2 & time3
# !_LC4_C18 & !_LC7_C18 & time3
# _LC4_C18 & !_LC7_C18 & time2 & !time3;
-- Node name is ':12' = 'time4'
-- Equation name is 'time4', location is LC2_C15, type is buried.
time4 = DFFE( _EQ004, GLOBAL( cp), GLOBAL( en3), VCC, VCC);
_EQ004 = !_LC2_C18 & !_LC7_C18 & time4
# _LC2_C18 & !_LC7_C18 & !time4;
-- Node name is ':11' = 'time5'
-- Equation name is 'time5', location is LC7_C15, type is buried.
time5 = DFFE( _EQ005, GLOBAL( cp), GLOBAL( en3), VCC, VCC);
_EQ005 = !_LC7_C18 & !time4 & time5
# !_LC2_C18 & !_LC7_C18 & time5
# _LC2_C18 & !_LC7_C18 & time4 & !time5;
-- Node name is '|LPM_ADD_SUB:115|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C18', type is buried
!_LC4_C18 = _LC4_C18~NOT;
_LC4_C18~NOT = LCELL( _EQ006);
_EQ006 = !time1
# !time0;
-- Node name is '|LPM_ADD_SUB:115|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C18', type is buried
_LC2_C18 = LCELL( _EQ007);
_EQ007 = time0 & time1 & time2 & time3;
-- Node name is ':9'
-- Equation name is '_LC6_C18', type is buried
_LC6_C18 = DFFE( _EQ008, GLOBAL( cp), GLOBAL( en3), VCC, VCC);
_EQ008 = !_LC8_C18 & time0 & time1 & !time2;
-- Node name is '~69~1'
-- Equation name is '~69~1', location is LC8_C18, type is buried.
-- synthesized logic cell
_LC8_C18 = LCELL( _EQ009);
_EQ009 = !time4
# !time5
# !time3;
-- Node name is ':69'
-- Equation name is '_LC7_C18', type is buried
!_LC7_C18 = _LC7_C18~NOT;
_LC7_C18~NOT = LCELL( _EQ010);
_EQ010 = time2
# !_LC4_C18
# _LC8_C18;
Project Information d:\vhdl3\count60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,873K
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