📄 fd_dmc3.rpt
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C: 1/ 96( 1%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl3\fd_dmc3.rpt
fd_dmc3
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 clk
Device-Specific Information: d:\vhdl3\fd_dmc3.rpt
fd_dmc3
** CLEAR SIGNALS **
Type Fan-out Name
DFF 6 qen1
DFF 6 qen2
DFF 6 qen3
Device-Specific Information: d:\vhdl3\fd_dmc3.rpt
fd_dmc3
** EQUATIONS **
clk : INPUT;
key1 : INPUT;
key2 : INPUT;
key3 : INPUT;
-- Node name is 'cpo1'
-- Equation name is 'cpo1', type is output
cpo1 = cp1;
-- Node name is 'cpo2'
-- Equation name is 'cpo2', type is output
cpo2 = cp2;
-- Node name is 'cpo3'
-- Equation name is 'cpo3', type is output
cpo3 = cp3;
-- Node name is ':13' = 'cp1'
-- Equation name is 'cp1', location is LC8_B16, type is buried.
cp1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, qen1);
_EQ001 = !jsp10 & !jsp13 & _LC7_B16;
-- Node name is ':20' = 'cp2'
-- Equation name is 'cp2', location is LC7_C17, type is buried.
cp2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, qen2);
_EQ002 = !jsp20 & !jsp23 & _LC8_C17;
-- Node name is ':27' = 'cp3'
-- Equation name is 'cp3', location is LC1_B2, type is buried.
cp3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, qen3);
_EQ003 = !jsp30 & !jsp33 & _LC8_B2;
-- Node name is ':12' = 'jsp10'
-- Equation name is 'jsp10', location is LC1_B23, type is buried.
jsp10 = DFFE(!jsp10, GLOBAL( clk), qen1, VCC, VCC);
-- Node name is ':11' = 'jsp11'
-- Equation name is 'jsp11', location is LC5_B16, type is buried.
jsp11 = DFFE( _EQ004, GLOBAL( clk), qen1, VCC, VCC);
_EQ004 = jsp10 & !jsp11 & jsp13
# !jsp10 & jsp11 & jsp13
# jsp10 & !jsp11 & _LC2_B16
# !jsp10 & jsp11 & _LC2_B16;
-- Node name is ':10' = 'jsp12'
-- Equation name is 'jsp12', location is LC4_B16, type is buried.
jsp12 = DFFE( _EQ005, GLOBAL( clk), qen1, VCC, VCC);
_EQ005 = !jsp10 & jsp12 & !_LC3_B16
# !jsp11 & jsp12 & !_LC3_B16
# jsp10 & jsp11 & !jsp12 & !_LC3_B16;
-- Node name is ':9' = 'jsp13'
-- Equation name is 'jsp13', location is LC6_B16, type is buried.
jsp13 = DFFE( _EQ006, GLOBAL( clk), qen1, VCC, VCC);
_EQ006 = jsp13 & _LC2_B16;
-- Node name is ':19' = 'jsp20'
-- Equation name is 'jsp20', location is LC2_C22, type is buried.
jsp20 = DFFE(!jsp20, GLOBAL( clk), qen2, VCC, VCC);
-- Node name is ':18' = 'jsp21'
-- Equation name is 'jsp21', location is LC5_C17, type is buried.
jsp21 = DFFE( _EQ007, GLOBAL( clk), qen2, VCC, VCC);
_EQ007 = jsp20 & !jsp21 & jsp23
# !jsp20 & jsp21 & jsp23
# jsp20 & !jsp21 & _LC2_C17
# !jsp20 & jsp21 & _LC2_C17;
-- Node name is ':17' = 'jsp22'
-- Equation name is 'jsp22', location is LC4_C17, type is buried.
jsp22 = DFFE( _EQ008, GLOBAL( clk), qen2, VCC, VCC);
_EQ008 = !jsp20 & jsp22 & !_LC3_C17
# !jsp21 & jsp22 & !_LC3_C17
# jsp20 & jsp21 & !jsp22 & !_LC3_C17;
-- Node name is ':16' = 'jsp23'
-- Equation name is 'jsp23', location is LC6_C17, type is buried.
jsp23 = DFFE( _EQ009, GLOBAL( clk), qen2, VCC, VCC);
_EQ009 = jsp23 & _LC2_C17;
-- Node name is ':26' = 'jsp30'
-- Equation name is 'jsp30', location is LC2_B7, type is buried.
jsp30 = DFFE(!jsp30, GLOBAL( clk), qen3, VCC, VCC);
-- Node name is ':25' = 'jsp31'
-- Equation name is 'jsp31', location is LC6_B2, type is buried.
jsp31 = DFFE( _EQ010, GLOBAL( clk), qen3, VCC, VCC);
_EQ010 = jsp30 & !jsp31 & jsp33
# !jsp30 & jsp31 & jsp33
# jsp30 & !jsp31 & _LC3_B2
# !jsp30 & jsp31 & _LC3_B2;
-- Node name is ':24' = 'jsp32'
-- Equation name is 'jsp32', location is LC5_B2, type is buried.
jsp32 = DFFE( _EQ011, GLOBAL( clk), qen3, VCC, VCC);
_EQ011 = !jsp30 & jsp32 & !_LC4_B2
# !jsp31 & jsp32 & !_LC4_B2
# jsp30 & jsp31 & !jsp32 & !_LC4_B2;
-- Node name is ':23' = 'jsp33'
-- Equation name is 'jsp33', location is LC7_B2, type is buried.
jsp33 = DFFE( _EQ012, GLOBAL( clk), qen3, VCC, VCC);
_EQ012 = jsp33 & _LC3_B2;
-- Node name is ':8' = 'qen1'
-- Equation name is 'qen1', location is LC1_B16, type is buried.
qen1 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !jsp13 & _LC2_B16 & qen1
# !jsp13 & key1 & _LC2_B16;
-- Node name is ':15' = 'qen2'
-- Equation name is 'qen2', location is LC1_C17, type is buried.
qen2 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !jsp23 & _LC2_C17 & qen2
# !jsp23 & key2 & _LC2_C17;
-- Node name is ':22' = 'qen3'
-- Equation name is 'qen3', location is LC2_B2, type is buried.
qen3 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !jsp33 & _LC3_B2 & qen3
# !jsp33 & key3 & _LC3_B2;
-- Node name is ':77'
-- Equation name is '_LC3_B16', type is buried
!_LC3_B16 = _LC3_B16~NOT;
_LC3_B16~NOT = LCELL( _EQ016);
_EQ016 = jsp13
# _LC2_B16;
-- Node name is '~154~1'
-- Equation name is '~154~1', location is LC7_B16, type is buried.
-- synthesized logic cell
_LC7_B16 = LCELL( _EQ017);
_EQ017 = !jsp11 & !jsp12;
-- Node name is ':196'
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = LCELL( _EQ018);
_EQ018 = !jsp12
# !jsp10
# !jsp11;
-- Node name is ':342'
-- Equation name is '_LC3_C17', type is buried
!_LC3_C17 = _LC3_C17~NOT;
_LC3_C17~NOT = LCELL( _EQ019);
_EQ019 = jsp23
# _LC2_C17;
-- Node name is '~419~1'
-- Equation name is '~419~1', location is LC8_C17, type is buried.
-- synthesized logic cell
_LC8_C17 = LCELL( _EQ020);
_EQ020 = !jsp21 & !jsp22;
-- Node name is ':461'
-- Equation name is '_LC2_C17', type is buried
_LC2_C17 = LCELL( _EQ021);
_EQ021 = !jsp22
# !jsp20
# !jsp21;
-- Node name is ':607'
-- Equation name is '_LC4_B2', type is buried
!_LC4_B2 = _LC4_B2~NOT;
_LC4_B2~NOT = LCELL( _EQ022);
_EQ022 = jsp33
# _LC3_B2;
-- Node name is '~684~1'
-- Equation name is '~684~1', location is LC8_B2, type is buried.
-- synthesized logic cell
_LC8_B2 = LCELL( _EQ023);
_EQ023 = !jsp31 & !jsp32;
-- Node name is ':726'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = LCELL( _EQ024);
_EQ024 = !jsp32
# !jsp30
# !jsp31;
Project Information d:\vhdl3\fd_dmc3.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 20,456K
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