📄 show.rpt
字号:
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 4/ 96( 4%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl3\show.rpt
show
** EQUATIONS **
di0 : INPUT;
di1 : INPUT;
di2 : INPUT;
di3 : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC6_B4;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC8_B2;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = !_LC2_B4;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC3_B4;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC5_B4;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = _LC1_B2;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = _LC2_B2;
-- Node name is ':55'
-- Equation name is '_LC3_B2', type is buried
!_LC3_B2 = _LC3_B2~NOT;
_LC3_B2~NOT = LCELL( _EQ001);
_EQ001 = di3
# !di0
# !di1
# !di2;
-- Node name is ':91'
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = LCELL( _EQ002);
_EQ002 = !di0 & !di1 & di2 & !di3;
-- Node name is ':115'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = LCELL( _EQ003);
_EQ003 = !di0 & di1 & !di2 & !di3;
-- Node name is ':127'
-- Equation name is '_LC1_B4', type is buried
!_LC1_B4 = _LC1_B4~NOT;
_LC1_B4~NOT = LCELL( _EQ004);
_EQ004 = di3
# !di0
# di1
# di2;
-- Node name is ':139'
-- Equation name is '_LC4_B4', type is buried
!_LC4_B4 = _LC4_B4~NOT;
_LC4_B4~NOT = LCELL( _EQ005);
_EQ005 = di3
# di0
# di1
# di2;
-- Node name is ':142'
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = LCELL( _EQ006);
_EQ006 = di3
# !di0 & !di2
# di0 & di1
# di1 & !di2
# di0 & di2;
-- Node name is ':162'
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = LCELL( _EQ007);
_EQ007 = !di2
# di3
# di0 & di1
# !di0 & !di1;
-- Node name is ':172'
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = LCELL( _EQ008);
_EQ008 = _LC5_B2
# _LC6_B2
# !_LC7_B2
# !_LC4_B2;
-- Node name is ':232'
-- Equation name is '_LC3_B4', type is buried
_LC3_B4 = LCELL( _EQ009);
_EQ009 = di1 & !di2 & !di3
# !di0 & !di2 & !di3
# !di0 & di1 & !di3
# di0 & !di1 & di2 & !di3
# !di0 & !di1 & !di2;
-- Node name is ':258'
-- Equation name is '_LC7_B4', type is buried
_LC7_B4 = LCELL( _EQ010);
_EQ010 = !di0 & !di1 & !di2 & di3
# !di0 & di1 & di2 & !di3;
-- Node name is ':262'
-- Equation name is '_LC5_B4', type is buried
_LC5_B4 = LCELL( _EQ011);
_EQ011 = !_LC1_B4 & _LC2_B4
# !_LC1_B4 & _LC7_B4
# _LC4_B4;
-- Node name is ':292'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ012);
_EQ012 = !_LC1_B4 & !_LC3_B2 & _LC4_B2
# _LC4_B4;
-- Node name is '~294~1'
-- Equation name is '~294~1', location is LC4_B2, type is buried.
-- synthesized logic cell
_LC4_B2 = LCELL( _EQ013);
_EQ013 = di3
# !di1
# di2;
-- Node name is '~324~1'
-- Equation name is '~324~1', location is LC7_B2, type is buried.
-- synthesized logic cell
!_LC7_B2 = _LC7_B2~NOT;
_LC7_B2~NOT = LCELL( _EQ014);
_EQ014 = _LC1_B4
# _LC4_B4;
-- Node name is ':324'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = LCELL( _EQ015);
_EQ015 = !_LC1_B4 & !_LC3_B2 & !_LC4_B4;
Project Information d:\vhdl3\show.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,334K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -