fd_dmc3.vhd

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library ieee;
use ieee.std_logic_1164.all;
entity fd_dmc3 is
 port(key1,key2,key3,clk:in std_logic;
      cpo1:out std_logic;
      cpo2:out std_logic;
      cpo3:out std_logic
      );
end fd_dmc3;
 architecture dmc of fd_dmc3 is
  signal qen1,cp1,cr1:std_logic;
  signal qen2,cp2,cr2:std_logic;
  signal qen3,cp3,cr3:std_logic;
  signal jsp1:integer range 0 to 15;
  signal jsp2:integer range 0 to 15;
  signal jsp3:integer range 0 to 15;
  begin
   d1:process(clk)
     begin 
      if qen1='0'then
       jsp1<=0;
       elsif(clk'event and clk='1')then
        if jsp1=7 then 
          jsp1<=0;
        else jsp1<=jsp1+1;
        end if;

        if jsp1=0 then
         cp1<='1';
        else
         cp1<='0';
        end if;
       --end if;
     
     end if;
     
        cpo1<=cp1;
    
     if jsp1<7 then 
      cr1<='1';
     else cr1<='0';
     end if;
end process d1;

c1:process(clk)
     begin
      if(clk'event and clk='1')then 
       if cr1='1' then
         if key1='1'then -- or key2='1'or key3='1'then
                 
           qen1<='1';
         else qen1<=qen1;
         end if;
       else qen1<='0';
       end if;
      end if;
end process c1;

d2:process(clk)
     begin 
      if qen2='0'then
       jsp2<=0;
       elsif(clk'event and clk='1')then
        if jsp2=7 then 
          jsp2<=0;
        else jsp2<=jsp2+1;
        end if;

        if jsp2=0 then
         cp2<='1';
        else
         cp2<='0';
        end if;
       --end if;
     
     end if;
     
        cpo2<=cp2;
    
     if jsp2<7 then 
      cr2<='1';
     else cr2<='0';
     end if;
end process d2;

c2:process(clk)
     begin
      if(clk'event and clk='1')then 
       if cr2='1' then
         if key2='1'then -- or key2='1'or key3='1'then
                 
           qen2<='1';
         else qen2<=qen2;
         end if;
       else qen2<='0';
       end if;
      end if;
end process c2;

d3:process(clk)
     begin 
      if qen3='0'then
       jsp3<=0;
       elsif(clk'event and clk='1')then
        if jsp3=7 then 
          jsp3<=0;
        else jsp3<=jsp3+1;
        end if;

        if jsp3=0 then
         cp3<='1';
        else
         cp3<='0';
        end if;
       --end if;
     
     end if;
     
        cpo3<=cp3;
    
     if jsp3<7 then 
      cr3<='1';
     else cr3<='0';
     end if;
end process d3;

c3:process(clk)
     begin
      if(clk'event and clk='1')then 
       if cr3='1' then
         if key3='1'then -- or key2='1'or key3='1'then
                 
           qen3<='1';
         else qen3<=qen3;
         end if;
       else qen3<='0';
       end if;
      end if;
end process c3;
end dmc;