dds.tan.qmsg

直接数字频率合成器

{ "Info" "ITDB_TH_RESULT" "lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[8\]~reg_ra3 phase\[3\] clk -1.300 ns memory " "Info: th for memory \"lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[8\]~reg_ra3\" (data pin = \"phase\[3\]\", clock pin = \"clk\") is -1.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to destination memory is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 99 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 99; CLK Node = 'clk'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "E:/My_Designs/max/dds.bdf" { { 304 -48 120 320 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[8\]~reg_ra3 2 MEM EC3_B 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = EC3_B; Fanout = 1; MEM Node = 'lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[8\]~reg_ra3'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "2.000 ns" { clk lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[8]~reg_ra3 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altrom.tdf" 86 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[8]~reg_ra3 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[8]~reg_ra3 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "2.000 ns + " "Info: + Micro hold delay of destination is 2.000 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altrom.tdf" 86 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.200 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns phase\[3\] 1 PIN PIN_1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_1; Fanout = 2; PIN Node = 'phase\[3\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "" { phase[3] } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "E:/My_Designs/max/dds.bdf" { { 0 -64 104 16 "phase\[8..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.900 ns) 5.400 ns lpm_add_sub0:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] 2 COMB LC8_B10 10 " "Info: 2: + IC(1.600 ns) + CELL(1.900 ns) = 5.400 ns; Loc. = LC8_B10; Fanout = 10; COMB Node = 'lpm_add_sub0:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.500 ns" { phase[3] lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.000 ns) 7.200 ns lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[8\]~reg_ra3 3 MEM EC3_B 1 " "Info: 3: + IC(1.800 ns) + CELL(0.000 ns) = 7.200 ns; Loc. = EC3_B; Fanout = 1; MEM Node = 'lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[8\]~reg_ra3'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "1.800 ns" { lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[8]~reg_ra3 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altrom.tdf" 86 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 52.78 % " "Info: Total cell delay = 3.800 ns ( 52.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns 47.22 % " "Info: Total interconnect delay = 3.400 ns ( 47.22 % )" {  } {  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "7.200 ns" { phase[3] lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[8]~reg_ra3 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "7.200 ns" { phase[3] phase[3]~out lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[8]~reg_ra3 } { 0.000ns 0.000ns 1.600ns 1.800ns } { 0.000ns 1.900ns 1.900ns 0.000ns } } }  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[8]~reg_ra3 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[8]~reg_ra3 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "7.200 ns" { phase[3] lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[8]~reg_ra3 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "7.200 ns" { phase[3] phase[3]~out lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[8]~reg_ra3 } { 0.000ns 0.000ns 1.600ns 1.800ns } { 0.000ns 1.900ns 1.900ns 0.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 08 10:23:59 2006 " "Info: Processing ended: Mon May 08 10:23:59 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}