📄 dds.tan.qmsg

📁 直接数字频率合成器
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[0\] register lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\] 96.15 MHz 10.4 ns Internal " "Info: Clock \"clk\" has Internal fmax of 96.15 MHz between source register \"lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[0\]\" and destination register \"lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\]\" (period= 10.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.200 ns + Longest register register " "Info: + Longest register to register delay is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[0\] 1 REG LC3_B10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B10; Fanout = 4; REG Node = 'lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[0\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "" { lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.900 ns) 2.700 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC5_B9 2 " "Info: 2: + IC(1.800 ns) + CELL(0.900 ns) = 2.700 ns; Loc. = LC5_B9; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "2.700 ns" { lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.900 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 3 COMB LC6_B9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 2.900 ns; Loc. = LC6_B9; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.200 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.100 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 4 COMB LC7_B9 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 3.100 ns; Loc. = LC7_B9; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.200 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.300 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 5 COMB LC8_B9 2 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 3.300 ns; Loc. = LC8_B9; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.200 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 4.000 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 6 COMB LC1_B11 2 " "Info: 6: + IC(0.500 ns) + CELL(0.200 ns) = 4.000 ns; Loc. = LC1_B11; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.700 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.200 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 7 COMB LC2_B11 2 " "Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 4.200 ns; Loc. = LC2_B11; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.200 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.400 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 8 COMB LC3_B11 2 " "Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 4.400 ns; Loc. = LC3_B11; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.200 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 5.500 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\] 9 COMB LC4_B11 1 " "Info: 9: + IC(0.000 ns) + CELL(1.100 ns) = 5.500 ns; Loc. = LC4_B11; Fanout = 1; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "1.100 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.900 ns) 8.200 ns lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\] 10 REG LC7_B12 4 " "Info: 10: + IC(1.800 ns) + CELL(0.900 ns) = 8.200 ns; Loc. = LC7_B12; Fanout = 4; REG Node = 'lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "2.700 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.100 ns 50.00 % " "Info: Total cell delay = 4.100 ns ( 50.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.100 ns 50.00 % " "Info: Total interconnect delay = 4.100 ns ( 50.00 % )" {  } {  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "8.200 ns" { lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.200 ns" { lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 1.800ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 0.900ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.100ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 99 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 99; CLK Node = 'clk'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "E:/My_Designs/max/dds.bdf" { { 304 -48 120 320 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\] 2 REG LC7_B12 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC7_B12; Fanout = 4; REG Node = 'lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "2.000 ns" { clk lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 99 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 99; CLK Node = 'clk'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "E:/My_Designs/max/dds.bdf" { { 304 -48 120 320 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[0\] 2 REG LC3_B10 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_B10; Fanout = 4; REG Node = 'lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[0\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "2.000 ns" { clk lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "8.200 ns" { lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.200 ns" { lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 1.800ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 0.900ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.100ns 0.900ns } } } { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\] freword\[0\] clk 9.700 ns register " "Info: tsu for register \"lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\]\" (data pin = \"freword\[0\]\", clock pin = \"clk\") is 9.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.300 ns + Longest pin register " "Info: + Longest pin to register delay is 12.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns freword\[0\] 1 PIN PIN_37 2 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_37; Fanout = 2; PIN Node = 'freword\[0\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "" { freword[0] } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "E:/My_Designs/max/dds.bdf" { { 88 -64 104 104 "freword\[8..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.900 ns) 6.800 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC5_B9 2 " "Info: 2: + IC(2.800 ns) + CELL(0.900 ns) = 6.800 ns; Loc. = LC5_B9; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.700 ns" { freword[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.000 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 3 COMB LC6_B9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 7.000 ns; Loc. = LC6_B9; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.200 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.200 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 4 COMB LC7_B9 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 7.200 ns; Loc. = LC7_B9; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.200 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.400 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 5 COMB LC8_B9 2 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 7.400 ns; Loc. = LC8_B9; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.200 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 8.100 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 6 COMB LC1_B11 2 " "Info: 6: + IC(0.500 ns) + CELL(0.200 ns) = 8.100 ns; Loc. = LC1_B11; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.700 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.300 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 7 COMB LC2_B11 2 " "Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 8.300 ns; Loc. = LC2_B11; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.200 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.500 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 8 COMB LC3_B11 2 " "Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 8.500 ns; Loc. = LC3_B11; Fanout = 2; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "0.200 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 9.600 ns lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\] 9 COMB LC4_B11 1 " "Info: 9: + IC(0.000 ns) + CELL(1.100 ns) = 9.600 ns; Loc. = LC4_B11; Fanout = 1; COMB Node = 'lpm_add_sub0:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "1.100 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.900 ns) 12.300 ns lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\] 10 REG LC7_B12 4 " "Info: 10: + IC(1.800 ns) + CELL(0.900 ns) = 12.300 ns; Loc. = LC7_B12; Fanout = 4; REG Node = 'lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "2.700 ns" { lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 58.54 % " "Info: Total cell delay = 7.200 ns ( 58.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.100 ns 41.46 % " "Info: Total interconnect delay = 5.100 ns ( 41.46 % )" {  } {  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "12.300 ns" { freword[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.300 ns" { freword[0] freword[0]~out lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 2.800ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 3.100ns 0.900ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.100ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 99 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 99; CLK Node = 'clk'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "E:/My_Designs/max/dds.bdf" { { 304 -48 120 320 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\] 2 REG LC7_B12 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC7_B12; Fanout = 4; REG Node = 'lpm_dff1:inst\|lpm_ff:lpm_ff_component\|dffs\[7\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "2.000 ns" { clk lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "12.300 ns" { freword[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.300 ns" { freword[0] freword[0]~out lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub0:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 2.800ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 3.100ns 0.900ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.100ns 0.900ns } } } { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk sinvalue\[3\] lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]~reg_ra0 22.100 ns memory " "Info: tco from clock \"clk\" to destination pin \"sinvalue\[3\]\" through memory \"lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]~reg_ra0\" is 22.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 99 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 99; CLK Node = 'clk'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "E:/My_Designs/max/dds.bdf" { { 304 -48 120 320 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]~reg_ra0 2 MEM EC3_C 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = EC3_C; Fanout = 1; MEM Node = 'lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]~reg_ra0'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "2.000 ns" { clk lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altrom.tdf" 86 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altrom.tdf" 86 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.700 ns + Longest memory pin " "Info: + Longest memory to pin delay is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]~reg_ra0 1 MEM EC3_C 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC3_C; Fanout = 1; MEM Node = 'lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]~reg_ra0'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "" { lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altrom.tdf" 86 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.700 ns) 8.700 ns lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]~mem_cell_ra0 2 MEM EC3_C 1 " "Info: 2: + IC(0.000 ns) + CELL(8.700 ns) = 8.700 ns; Loc. = EC3_C; Fanout = 1; MEM Node = 'lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]~mem_cell_ra0'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "8.700 ns" { lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~mem_cell_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altrom.tdf" 86 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 10.700 ns lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\] 3 MEM EC3_C 1 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 10.700 ns; Loc. = EC3_C; Fanout = 1; MEM Node = 'lpm_rom0:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "2.000 ns" { lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~mem_cell_ra0 lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3] } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altrom.tdf" 86 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(3.900 ns) 17.700 ns sinvalue\[3\] 4 PIN PIN_50 0 " "Info: 4: + IC(3.100 ns) + CELL(3.900 ns) = 17.700 ns; Loc. = PIN_50; Fanout = 0; PIN Node = 'sinvalue\[3\]'" {  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "7.000 ns" { lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3] sinvalue[3] } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "E:/My_Designs/max/dds.bdf" { { 296 464 640 312 "sinvalue\[9..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.600 ns 82.49 % " "Info: Total cell delay = 14.600 ns ( 82.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns 17.51 % " "Info: Total interconnect delay = 3.100 ns ( 17.51 % )" {  } {  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "17.700 ns" { lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~mem_cell_ra0 lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3] sinvalue[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~mem_cell_ra0 lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3] sinvalue[3] } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 8.700ns 2.000ns 3.900ns } } }  } 0}  } { { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "3.900 ns" { clk lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "E:/My_Designs/max/db/dds_cmp.qrpt" "" { Report "E:/My_Designs/max/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "E:/My_Designs/max/db/dds.quartus_db" { Floorplan "E:/My_Designs/max/" "" "17.700 ns" { lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~mem_cell_ra0 lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3] sinvalue[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~mem_cell_ra0 lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3] sinvalue[3] } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 8.700ns 2.000ns 3.900ns } } }  } 0}
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