dds.sim.vwf

来自「直接数字频率合成器」· VWF 代码 · 共 2,106 行 · 第 1/3 页

VWF
2,106 行
字号
123
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	PRINT_OPTIONS = "Print_options_version 6\
range_start 0ps\
range_end 5.0us\
width 1\
names_percentage 25\
comments 1\
grid_lines 1\
time_bars 1\
name_every_page 0\
expand_groups 0\
print_all 1";
	SIMULATION_TIME = 5000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("freword")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 9;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("freword[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "freword";
}

SIGNAL("freword[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "freword";
}

SIGNAL("freword[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "freword";
}

SIGNAL("freword[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "freword";
}

SIGNAL("freword[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "freword";
}

SIGNAL("freword[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "freword";
}

SIGNAL("freword[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "freword";
}

SIGNAL("freword[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "freword";
}

SIGNAL("freword[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "freword";
}

SIGNAL("phase")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 9;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("phase[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "phase";
}

SIGNAL("phase[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "phase";
}

SIGNAL("phase[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "phase";
}

SIGNAL("phase[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "phase";
}

SIGNAL("phase[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "phase";
}

SIGNAL("phase[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "phase";
}

SIGNAL("phase[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "phase";
}

SIGNAL("phase[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "phase";
}

SIGNAL("phase[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "phase";
}

SIGNAL("sinvalue")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 10;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("sinvalue[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sinvalue";
}

SIGNAL("sinvalue[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sinvalue";
}

SIGNAL("sinvalue[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sinvalue";
}

SIGNAL("sinvalue[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sinvalue";
}

SIGNAL("sinvalue[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sinvalue";
}

SIGNAL("sinvalue[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sinvalue";
}

SIGNAL("sinvalue[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sinvalue";
}

SIGNAL("sinvalue[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sinvalue";
}

SIGNAL("sinvalue[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sinvalue";
}

SIGNAL("sinvalue[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sinvalue";
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 500;
			LEVEL 0 FOR 5.0;
			LEVEL 1 FOR 5.0;
		}
	}
}

TRANSITION_LIST("freword[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("freword[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("freword[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("freword[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("freword[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("freword[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("freword[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("freword[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("freword[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 5000.0;
	}
}

TRANSITION_LIST("phase[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("phase[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("phase[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("phase[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("phase[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("phase[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("phase[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("phase[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("phase[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 5000.0;
	}
}

TRANSITION_LIST("sinvalue[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5000.0;
	}
}

TRANSITION_LIST("sinvalue[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5.0;
		LEVEL 1 FOR 2550.0;
		LEVEL 0 FOR 2445.0;
	}
}

TRANSITION_LIST("sinvalue[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 5.0;
		LEVEL 0 FOR 430.0;
		LEVEL 1 FOR 1690.0;
		LEVEL 0 FOR 430.0;
		LEVEL 1 FOR 430.0;
		LEVEL 0 FOR 1710.0;
		LEVEL 1 FOR 305.0;
	}
}

TRANSITION_LIST("sinvalue[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 5.0;
		LEVEL 0 FOR 210.0;
		LEVEL 1 FOR 220.0;
		LEVEL 0 FOR 260.0;
		LEVEL 1 FOR 1170.0;
		LEVEL 0 FOR 260.0;
		LEVEL 1 FOR 220.0;
		LEVEL 0 FOR 210.0;
		LEVEL 1 FOR 210.0;
		LEVEL 0 FOR 220.0;
		LEVEL 1 FOR 260.0;
		LEVEL 0 FOR 1190.0;
		LEVEL 1 FOR 260.0;
		LEVEL 0 FOR 220.0;
		LEVEL 1 FOR 85.0;
	}
}

TRANSITION_LIST("sinvalue[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 5.0;
		LEVEL 0 FOR 100.0;
		LEVEL 1 FOR 110.0;
		LEVEL 0 FOR 100.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 120.0;
		LEVEL 1 FOR 140.0;
		LEVEL 0 FOR 190.0;
		LEVEL 1 FOR 790.0;
		LEVEL 0 FOR 190.0;
		LEVEL 1 FOR 140.0;
		LEVEL 0 FOR 120.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 100.0;
		LEVEL 1 FOR 110.0;
		LEVEL 0 FOR 100.0;
		LEVEL 1 FOR 100.0;
		LEVEL 0 FOR 110.0;
		LEVEL 1 FOR 110.0;
		LEVEL 0 FOR 110.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 140.0;
		LEVEL 1 FOR 180.0;
		LEVEL 0 FOR 830.0;
		LEVEL 1 FOR 180.0;
		LEVEL 0 FOR 140.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 110.0;
		LEVEL 1 FOR 110.0;
		LEVEL 0 FOR 85.0;
	}
}

TRANSITION_LIST("sinvalue[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 5.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 60.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 50.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 60.0;
			LEVEL 1 FOR 60.0;
		}
		LEVEL 0 FOR 70.0;
		LEVEL 1 FOR 70.0;
		LEVEL 0 FOR 90.0;
		LEVEL 1 FOR 100.0;
		LEVEL 0 FOR 120.0;
		LEVEL 1 FOR 550.0;
		LEVEL 0 FOR 120.0;
		LEVEL 1 FOR 100.0;
		LEVEL 0 FOR 90.0;
		LEVEL 1 FOR 70.0;
		LEVEL 0 FOR 70.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 60.0;
			LEVEL 0 FOR 60.0;
		}
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 60.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 50.0;
			LEVEL 1 FOR 50.0;
		}
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 60.0;
		LEVEL 0 FOR 50.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 50.0;
			LEVEL 0 FOR 60.0;
		}
		LEVEL 1 FOR 60.0;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 70.0;
		LEVEL 0 FOR 70.0;
		LEVEL 1 FOR 90.0;
		LEVEL 0 FOR 90.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 590.0;
123

dds.sim.vwf - 源码说明

本页面展示了「直接数字频率合成器」中的 dds.sim.vwf 源码文件，采用 VWF 编程语言编写，共 2,106 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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