dds_v.sdo

来自「直接数字频率合成器」· SDO 代码 · 共 1,992 行 · 第 1/5 页

SDO
1,992 行
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12345
        (IOPATH raddr[6] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[7] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[8] dataout (2000:2000:2000) (2000:2000:2000))
      )
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[6\].raddrreg_0)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[6\].raddrreg_1)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[6\].raddrreg_2)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[6\].raddrreg_3)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[6\].raddrreg_4)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[6\].raddrreg_5)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[6\].raddrreg_6)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[6\].raddrreg_7)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[6\].raddrreg_8)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_mem")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[6\].flexmem)
    (DELAY
      (ABSOLUTE
        (PORT raddr[0] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[1] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[2] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[3] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[4] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[5] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[6] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[7] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[8] (8700:8700:8700) (8700:8700:8700))
        (IOPATH raddr[0] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[1] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[2] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[3] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[4] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[5] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[6] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[7] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[8] dataout (2000:2000:2000) (2000:2000:2000))
      )
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[5\].raddrreg_0)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[5\].raddrreg_1)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[5\].raddrreg_2)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[5\].raddrreg_3)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[5\].raddrreg_4)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[5\].raddrreg_5)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[5\].raddrreg_6)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[5\].raddrreg_7)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[5\].raddrreg_8)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_mem")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[5\].flexmem)
    (DELAY
      (ABSOLUTE
        (PORT raddr[0] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[1] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[2] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[3] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[4] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[5] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[6] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[7] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[8] (8700:8700:8700) (8700:8700:8700))
        (IOPATH raddr[0] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[1] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[2] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[3] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[4] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[5] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[6] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[7] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[8] dataout (2000:2000:2000) (2000:2000:2000))
      )
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[4\].raddrreg_0)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[4\].raddrreg_1)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[4\].raddrreg_2)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[4\].raddrreg_3)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[4\].raddrreg_4)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
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dds_v.sdo - 源码说明

本页面展示了「直接数字频率合成器」中的 dds_v.sdo 源码文件，采用 SDO 编程语言编写，共 1,992 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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