📄 dds_v.sdo

📁 直接数字频率合成器
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    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[9\].raddrreg_6)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[9\].raddrreg_7)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[9\].raddrreg_8)
    (DELAY
      (ABSOLUTE
        (PORT D (2500:2500:2500) (2500:2500:2500))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_mem")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[9\].flexmem)
    (DELAY
      (ABSOLUTE
        (PORT raddr[0] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[1] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[2] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[3] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[4] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[5] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[6] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[7] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[8] (8700:8700:8700) (8700:8700:8700))
        (IOPATH raddr[0] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[1] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[2] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[3] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[4] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[5] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[6] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[7] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[8] dataout (2000:2000:2000) (2000:2000:2000))
      )
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[8\].raddrreg_0)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[8\].raddrreg_1)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[8\].raddrreg_2)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[8\].raddrreg_3)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[8\].raddrreg_4)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[8\].raddrreg_5)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[8\].raddrreg_6)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[8\].raddrreg_7)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[8\].raddrreg_8)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_mem")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[8\].flexmem)
    (DELAY
      (ABSOLUTE
        (PORT raddr[0] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[1] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[2] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[3] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[4] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[5] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[6] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[7] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[8] (8700:8700:8700) (8700:8700:8700))
        (IOPATH raddr[0] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[1] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[2] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[3] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[4] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[5] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[6] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[7] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[8] dataout (2000:2000:2000) (2000:2000:2000))
      )
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[7\].raddrreg_0)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[7\].raddrreg_1)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[7\].raddrreg_2)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[7\].raddrreg_3)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[7\].raddrreg_4)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[7\].raddrreg_5)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[7\].raddrreg_6)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[7\].raddrreg_7)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "dffe")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[7\].raddrreg_8)
    (DELAY
      (ABSOLUTE
        (PORT D (1800:1800:1800) (1800:1800:1800))
        (PORT CLK (2000:2000:2000) (2000:2000:2000))
        (IOPATH (posedge CLK) Q (500:500:500) (500:500:500))
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (1500:1500:1500))
      (HOLD D (posedge CLK) (2000:2000:2000))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_mem")
    (INSTANCE inst3\|lpm_rom_component\|srom\|segment\[0\]\[7\].flexmem)
    (DELAY
      (ABSOLUTE
        (PORT raddr[0] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[1] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[2] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[3] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[4] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[5] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[6] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[7] (8700:8700:8700) (8700:8700:8700))
        (PORT raddr[8] (8700:8700:8700) (8700:8700:8700))
        (IOPATH raddr[0] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[1] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[2] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[3] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[4] dataout (2000:2000:2000) (2000:2000:2000))
        (IOPATH raddr[5] dataout (2000:2000:2000) (2000:2000:2000))
💿 文件大小 310 K
👤 上传用户 xufengping716
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#数字频率合成器
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