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<p align="left"> 目 录</p>
<img SRC="../../images/T.gif"><img SRC="../../images/nfolder.gif"><a href="y312448wz.pdf" target="mainFrame">文摘</a><br>
<img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y312448zye.pdf" target="mainFrame">英文文摘</a><br>
<img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480001.pdf" target="mainFrame">第一章绪论</a><br><%BOF%>
<img SRC="../../images/H.gif"><img SRC="../../images/ofolder.gif" ID="Out2" CLASS="Outline" STYLE="cursor:hand"><a href="y3124480002.pdf" target="mainFrame">第二章基于VHDL的TOP-DOWN设计方法</a><br>
<div ID="Out2d">
<img SRC="../../images/I.gif"><img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480003.pdf" target="mainFrame">§2.1自顶向下(TOP-DOWN)的设计方法</a><br>
<img SRC="../../images/I.gif"><img SRC="../../images/L.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480004.pdf" target="mainFrame">§2.2 VHDL在专用集成电路仿真中的应用</a><br>
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<img SRC="../../images/H.gif"><img SRC="../../images/ofolder.gif" ID="Out3" CLASS="Outline" STYLE="cursor:hand"><a href="y3124480005.pdf" target="mainFrame">第三章SDH同步数字体系的介绍</a><br>
<div ID="Out3d">
<img SRC="../../images/I.gif"><img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480006.pdf" target="mainFrame">§3.1同步数字体制相关知识</a><br>
<img SRC="../../images/I.gif"><img SRC="../../images/L.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480007.pdf" target="mainFrame">§3.2 SADM2芯片功能简介</a><br>
</div>
<img SRC="../../images/H.gif"><img SRC="../../images/ofolder.gif" ID="Out4" CLASS="Outline" STYLE="cursor:hand"><a href="y3124480008.pdf" target="mainFrame">第四章去映射去同步电路的VDHL设计</a><br>
<div ID="Out4d">
<img SRC="../../images/I.gif"><img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480009.pdf" target="mainFrame">§4.1 TU接受和终接以及去填充电路的设计</a><br>
<img SRC="../../images/I.gif"><img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480010.pdf" target="mainFrame">§4.2先进先出缓存器(FIFO)的设计</a><br>
<img SRC="../../images/I.gif"><img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480011.pdf" target="mainFrame">§4.3比特泄漏去同步电路</a><br>
<img SRC="../../images/I.gif"><img SRC="../../images/L.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480012.pdf" target="mainFrame">§4.4 HDB3编解码电路的设计</a><br>
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<img SRC="../../images/H.gif"><img SRC="../../images/ofolder.gif" ID="Out5" CLASS="Outline" STYLE="cursor:hand"><a href="y3124480013.pdf" target="mainFrame">第五章全数字锁相环(ADPLL)的VHDL设计</a><br>
<div ID="Out5d">
<img SRC="../../images/I.gif"><img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480014.pdf" target="mainFrame">§5.1数字鉴频鉴相器的设计</a><br>
<img SRC="../../images/I.gif"><img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480015.pdf" target="mainFrame">§5.2数字环路滤波电路的设计</a><br>
<img SRC="../../images/I.gif"><img SRC="../../images/L.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480016.pdf" target="mainFrame">§5.3数控振荡器(DCO)的设计</a><br>
</div>
<img SRC="../../images/H.gif"><img SRC="../../images/ofolder.gif" ID="Out6" CLASS="Outline" STYLE="cursor:hand"><a href="y3124480017.pdf" target="mainFrame">第六章SADM2芯片的ASIC设计与实现</a><br>
<div ID="Out6d">
<img SRC="../../images/I.gif"><img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480018.pdf" target="mainFrame">§6.1 COMPASS的ASIC设计流程</a><br>
<img SRC="../../images/I.gif"><img SRC="../../images/L.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480019.pdf" target="mainFrame">§6.2标准单元布局布线及后仿真工作的说明</a><br>
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<img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480020.pdf" target="mainFrame">结束语</a><br><%EOF%>
<img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480021.pdf" target="mainFrame">致谢</a><br>
<img SRC="../../images/L.gif"><img SRC="../../images/nfolder.gif"><a href="y3124480022.pdf" target="mainFrame">参考文献</a><br>
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