spi_master.v

基于CPLD/FPGA的SPI控制的IP核的实现spi_master

//**********************SPI总线系统设计*********************//
module spi_master(addr,addr_high,ale_n,clk,miso,psen_n,rd_n,reset,ss_in_n,wr_n,mosi,ss_n,DATA,int_n,rcv_full,sck,xmit_empty);
input [7:0]addr,addr_high;
input ale_n,clk,miso,psen_n,rd_n,reset,ss_in_n,wr_n;
output mosi;
output [7:0]ss_n;
inout [7:0]DATA;
inout int_n,rcv_full,sck,xmit_empty;

wire [7:0]ss_n;
wire [1:0]clkdiv;
wire cpha,cpol,mosi,done,rcv_cpol,rcv_full_reset,rcv_load,spien,ss_in_int,
			ss_n_int,start,xmit_empty_reset,int_n,rcv_full,sck,xmit_empty;

spi_interface m6(.clk(clk),.clkdiv(clkdiv),.cpha(cpha),.cpol(cpol),.miso(miso),
		 .rcv_cpol(rcv_cpol),.rcv_full_reset(rcv_full_reset),.reset(spien),
		 .ss_in_n(ss_in_n),.ss_mask_reg(spissr),.start(start),.xmit_data(spitr),
		 .xmit_empty_reset(xmit_empty_reset),.rcv_load(rcv_load),.sck(sck),
		 .ss_in_int(ss_in_int),.ss_n_int(ss_n_int),.xmit_empty(xmit_empty),
		 .done(done),.mosi(mosi),.rcv_data(rcv_data),.rcv_full(rcv_full),.ss_n(ss_n));
								 
uC_interface m7(.addr(addr),.addr_high(addr_high),.ale_n(ale_n),.clk(clk),.done(done),
		.psen_n(psen_n),.rcv_full(rcv_full),.rcv_load(rcv_load),.rd_n(rd_n),
		.receive_data(rcv_data),.reset(reset),.ss_in_int(ss_in_int),.ss_n(ss_n_int),.wr_n(wr_n),
		.xmit_empty(xmit_empty),.DATA(DATA),.clkdiv(clkdiv),.cpha(cpha),.cpol(cpol),
		.int_n(int_n),.rcv_cpol(rcv_cpol),.rcv_full_reset(rcv_full_reset),.spien(spien),
		.spissr(spissr),.spitr(spitr),.start(start),.xmit_empty_reset(xmit_empty_reset));
								
endmodule