📄 stage1_solution.mdl
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xl_use_estimator_area off
est_options "Estimate"
xl_estimator_area "[29 43 0 20 18 0 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "resource_estimator"
block_version "8.2.02"
sg_icon_stat "53,53,-1,-1,blue,white,0,07734"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 53 53 0 ],[0 0 53 53 ],[0.98 0.96 0.92]);\npatch([13 4 16 4 13 27 31 3"
"5 50 38 27 19 31 19 27 38 50 35 31 27 13 ],[6 15 27 39 48 48 44 48 48 36 47 3"
"9 27 15 7 18 6 6 10 6 6 ],[0.77 0.82 0.91]);\nplot([0 0 53 53 0 ],[0 53 53 0 "
"0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin "
"icon text');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Terminator
Name "Terminator1"
Position [940, 245, 960, 265]
}
Block {
BlockType Terminator
Name "Terminator2"
Position [940, 345, 960, 365]
}
Block {
BlockType Reference
Name "WaveScope"
Ports []
Position [72, 48, 145, 104]
UserDataPersistent on
UserData "DataTag1"
SourceBlock "xbsIndex_r4/WaveScope"
SourceType "WaveScope Block"
infoedit "WaveScope"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "wavescope"
block_version "8.2.02"
sg_icon_stat "0,0,-1,-1,white,blue,0,07734"
sg_blockgui_xml "<!-- * Copyright (c) 2005, Xilinx, Inc. All "
"Rights Reserved. --><!-- * Reproduction or reuse, in any form, w"
"ithout the explicit written --><!-- * consent of Xilinx, Inc., is strictly"
" prohibited. --><sysgenblock has_userdata=\"true\" block_typ"
"e=\"wavescope\" simulinkname=\"WaveScope\" >\n <initialization file=\"xlwaves"
"cope_init.m\" />\n <icon width=\"71\" height=\"62\" file=\"wavescope_icon.m\""
" />\n <sfunction name=\"xlpermissive\" />\n <callbacks InitFcn=\"xlRegisterHa"
"ndles(gcbh);\" DeleteFcn=\"fig_name = [ get_param(gcbh,'Parent') , '/', get_p"
"aram(gcbh,'Name') ];\\nscopehandle = findobj('Name',fig_name);\\nif scopehand"
"le\\n close(scopehandle);\\nend\" OpenFcn=\"xlWaveScope(gcbh);\" ModelCloseF"
"cn=\"fig_name = [ get_param(gcbh,'Parent') , '/', get_param(gcbh,'Name') ];\\"
"nscopehandle = findobj('Name',fig_name);\\nif scopehandle\\n close(scopehand"
"le);\\nend\" DestroyFcn=\"fig_name = [ get_param(gcbh,'Parent') , '/', get_pa"
"ram(gcbh,'Name') ];\\nscopehandle = findobj('Name',fig_name);\\nif scopehandl"
"e\\n close(scopehandle);\\nend\" PreSaveFcn=\"xlRegisterHandles(gcbh);\\n\" "
"CopyFcn=\"xlWaveScopeCopyFcn(gcbh);\\n\" StopFcn=\"userdata=get_param(gcbh,'u"
"serdata');\\nif(isfield(userdata,'RunAtEndOfSim')&&strcmp(userdata.Ru"
"nAtEndOfSim,'on'))\\n xlWaveScope(gcbh);\\nend\" />\n <libraries>\n <librar"
"y name=\"xbsIndex\" />\n <library name=\"xbsTools\" />\n </libraries>\n <blo"
"ckgui label=\"WaveScope\" >\n <editbox evaluate=\"false\" multi_line=\"true"
"\" name=\"infoedit\" read_only=\"true\" default=\"WaveScope\" />\n <hiddenva"
"r name=\"ShowPortLabels\" />\n </blockgui>\n</sysgenblock>\n"
}
Block {
BlockType Reference
Name "delay_F"
Ports [1, 1]
Position [795, 239, 820, 271]
NamePlacement "alternate"
SourceBlock "xbsIndex_r4/Delay"
SourceType "Xilinx Delay Block"
infoedit "Hardware notes: A delay line is a chain, each l"
"ink of which is an SRL16 followed by a flip-flop. If register retiming is ena"
"bled, the delay line is a chain of flip-flops."
en off
latency "1"
dbl_ovrd off
reg_retiming off
xl_use_area off
xl_area "[4 8 0 0 0 0 0]"
has_advanced_control "0"
sggui_pos "20,20,356,256"
block_type "delay"
block_version "8.2.02"
sg_icon_stat "25,32,1,1,white,blue,0,fc531c0e"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 25 25 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([6 2 8 2 6 13 15 17 2"
"4 18 13 9 14 9 13 18 24 17 15 13 6 ],[6 10 16 22 26 26 24 26 26 20 25 21 16 1"
"1 7 12 6 6 8 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 25 25 0 ],[0 32 32 0 0 ]);\n"
"fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te"
"xt');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en"
"d icon text');\n"
}
Block {
BlockType Reference
Name "delay_start"
Ports [1, 1]
Position [175, 319, 200, 351]
NamePlacement "alternate"
SourceBlock "xbsIndex_r4/Delay"
SourceType "Xilinx Delay Block"
infoedit "Hardware notes: A delay line is a chain, each l"
"ink of which is an SRL16 followed by a flip-flop. If register retiming is ena"
"bled, the delay line is a chain of flip-flops."
en off
latency "1"
dbl_ovrd off
reg_retiming off
xl_use_area off
xl_area "[1 1 0 0 0 0 0]"
has_advanced_control "0"
sggui_pos "20,20,356,256"
block_type "delay"
block_version "8.2.02"
sg_icon_stat "25,32,1,1,white,blue,0,fc531c0e"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 25 25 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([6 2 8 2 6 13 15 17 2"
"4 18 13 9 14 9 13 18 24 17 15 13 6 ],[6 10 16 22 26 26 24 26 26 20 25 21 16 1"
"1 7 12 6 6 8 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 25 25 0 ],[0 32 32 0 0 ]);\n"
"fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te"
"xt');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en"
"d icon text');\n"
}
Block {
BlockType Reference
Name "n"
Ports [1, 1]
Position [85, 170, 125, 190]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Unsigned"
n_bits "W"
bin_pt "0"
quantization "Round (unbiased: +/- Inf)"
overflow "Wrap"
period "Ts"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{'V16'}"
xl_use_area off
xl_area "[0 0 0 0 8 0 0]"
has_advanced_control "0"
sggui_pos "20,20,356,432"
block_type "gatewayin"
block_version "8.2.02"
sg_icon_stat "40,20,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 40 40 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([14 11 16 11 14 19 20"
" 21 27 23 19 16 21 16 19 23 27 21 20 19 14 ],[2 5 10 15 18 18 17 18 18 14 18 "
"15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 40 40 0 ],[0 20 20 0 0 "
"]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ic"
"on text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','t"
"exmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMME"
"NT: end icon text');\n"
Port {
PortNumber 1
Name "n"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "start"
Ports [1, 1]
Position [90, 324, 130, 346]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Boolean"
n_bits "W"
bin_pt "0"
quantization "Round (unbiased: +/- Inf)"
overflow "Wrap"
period "Ts"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{'V16'}"
xl_use_area off
xl_area "[0 0 0 0 1 0 0]"
has_advanced_control "0"
sggui_pos "20,20,356,432"
block_type "gatewayin"
block_version "8.2.02"
sg_icon_stat "40,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 40 40 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([14 10 15 10 14 20 22"
" 24 30 25 20 17 23 17 20 25 30 24 22 20 14 ],[2 6 11 16 20 20 18 20 20 15 20 "
"17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 40 40 0 ],[0 22 22 0 0 "
"]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ic"
"on text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','t"
"exmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMME"
"NT: end icon text');\n"
Port {
PortNumber 1
Name "start"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "valid"
Ports [1, 1]
Position [850, 344, 895, 366]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{'F9'}"
xl_use_area off
xl_area "[0 0 0 0 1 0 0]"
has_advanced_control "0"
sggui_pos "20,20,356,330"
block_type "gatewayout"
block_version "8.2.02"
sg_icon_stat "45,22,1,1,white,yellow,0,f0cec300"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 45 45 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([17 13 18 13 17 23 25"
" 27 33 28 23 20 26 20 23 28 33 27 25 23 17 ],[2 6 11 16 20 20 18 20 20 15 20 "
"17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 22 22 0 0 "
"]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ic"
"on text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_la"
"bel('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMM"
"ENT: end icon text');\n"
Port {
PortNumber 1
Name "valid"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Line {
SrcBlock "From\nWorkspace1"
SrcPort 1
DstBlock "n"
DstPort 1
}
Line {
SrcBlock "From\nWorkspace2"
SrcPort 1
DstBlock "start"
DstPort 1
}
Line {
Name "n"
Labels [0, 0]
SrcBlock "n"
SrcPort 1
DstBlock "Register_n"
DstPort 1
}
Line {
Name "i"
Labels [0, 0]
SrcBlock "Counter"
SrcPort 1
Points [0, 0]
DstBlock "Relational"
DstPort 2
}
Line {
Name "n_latch"
Labels [0, 0]
SrcBlock "Register_n"
SrcPort 1
Points [185, 0; 0, 145]
DstBlock "Relational"
DstPort 1
}
Line {
Name "F(n)"
Labels [2, 0]
SrcBlock "Register_F(n)"
SrcPort 1
Points [0, 0; 25, 0]
Branch {
Points [0, -85; -185, 0]
Branch {
Labels [1, 1]
Points [0, 40]
DstBlock "AddSub"
DstPort 1
}
Branch {
Points [-155, 0; 0, 55]
DstBlock "Register_F(n-1)"
DstPort 1
}
}
Branch {
DstBlock "delay_F"
DstPort 1
}
}
Line {
Name "F(n+1)"
Labels [2, 1]
SrcBlock "AddSub"
SrcPort 1
Points [0, 0]
DstBlock "Register_F(n)"
DstPort 1
}
Line {
Name "F(n-1)"
Labels [1, 1]
SrcBlock "Register_F(n-1)"
SrcPort 1
DstBlock "AddSub"
DstPort 2
}
Line {
Name "start"
Labels [2, 0]
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