📄 stage1_solution.mdl
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infoedit " System Generator"
xilinxfamily "Spartan3E"
part "xc3s500e"
speed "-4"
package "fg320"
synthesis_tool "XST"
directory "./ngc_netlist"
testbench off
simulink_period "Ts"
sysclk_period "20"
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trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
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eval_field "0"
has_advanced_control "0"
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");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ico"
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sg_blockgui_xml "<!-- * Copyright (c) 2005, Xilinx, Inc. All "
"Rights Reserved. --><!-- * Reproduction or reuse, in any form, w"
"ithout the explicit written --><!-- * consent of Xilinx, Inc., is strictly"
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" <library name=\"xbsIndex\" />\n <library name=\"xbsBasic\" />\n <library "
"name=\"xbsTools\" />\n </libraries>\n <subsystem_model file=\"system_generato"
"r_subsystem.mdl\" />\n <blockgui label=\"Xilinx System Generator\" >\n <edit"
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" evaluate=\"false\" name=\"speed\" default=\"-10\" label=\"Speed\" />\n <edi"
"tbox evaluate=\"false\" name=\"package\" default=\"ff668\" label=\"Package\" "
"/>\n <listbox evaluate=\"true\" name=\"synthesis_tool\" default=\"XST\" labe"
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"<item value=\"Precision\" />\n </listbox>\n <editbox evaluate=\"false\" nam"
"e=\"directory\" default=\"./netlist\" label=\"Target directory\" />\n <check"
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"/>\n <editbox evaluate=\"true\" name=\"simulink_period\" default=\"1\" label"
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"lock Masks\" />\n <item value=\"Everywhere Available\" />\n <item value="
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BlockType Reference
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SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
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