📄 stage3_3175133_zhang.mdl
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"/>\n <editbox evaluate=\"true\" name=\"simulink_period\" default=\"1\" label"
"=\"Simulink period\" />\n <editbox evaluate=\"true\" name=\"sysclk_period\" "
"default=\"10\" label=\"System clock period\" />\n <checkbox evaluate=\"true"
"\" name=\"incr_netlist\" default=\"off\" label=\"Incremental netlisting\" />"
"\n <listbox evaluate=\"true\" name=\"trim_vbits\" default=\"Everywhere in Su"
"bSystem\" label=\"Trim valid bits\" >\n <item value=\"According to Block Ma"
"sks\" />\n <item value=\"Everywhere in SubSystem\" />\n <item value=\"No "
"Where in SubSystem\" />\n </listbox>\n <listbox evaluate=\"true\" name=\"db"
"l_ovrd\" default=\"According to Block Masks\" label=\"Override with doubles\""
" >\n <item value=\"According to Block Masks\" />\n <item value=\"Everywhe"
"re in SubSystem\" />\n <item value=\"No Where in SubSystem\" />\n </listbo"
"x>\n <listbox evaluate=\"true\" name=\"core_generation\" default=\"According"
" to Block Masks\" label=\"Generate cores\" >\n <item value=\"According to B"
"lock Masks\" />\n <item value=\"Everywhere Available\" />\n <item value="
"\"Not Needed - Already Generated\" />\n </listbox>\n <checkbox evaluate=\"t"
"rue\" name=\"run_coregen\" default=\"off\" label=\"Run CoreGen\" />\n <check"
"box evaluate=\"true\" name=\"deprecated_control\" default=\"off\" label=\"Sho"
"w deprecated controls\" />\n <hiddenvar evaluate=\"true\" name=\"eval_field"
"\" default=\"0\" />\n </blockgui>\n</sysgenblock>\n"
}
Block {
BlockType Reference
Name "A"
Ports [1, 1]
Position [120, 145, 160, 165]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Unsigned"
n_bits "W"
bin_pt "0"
quantization "Round (unbiased: +/- Inf)"
overflow "Wrap"
period "Ts"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{'V16'}"
xl_use_area off
xl_area "[0 0 0 0 16 0 0]"
has_advanced_control "0"
sggui_pos "20,20,417,435"
block_type "gatewayin"
block_version "8.2.02"
sg_icon_stat "40,20,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33"
" 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 "
"15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 65 65 0 ],[0 20 20 0 0 "
"]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ic"
"on text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','t"
"exmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMME"
"NT: end icon text');\n"
Port {
PortNumber 1
Name "A"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "AddSub"
Ports [2, 1]
Position [485, 302, 540, 373]
NamePlacement "alternate"
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Subtraction"
use_carryin off
use_carryout off
en off
latency "0"
precision "User Defined"
arith_type "Unsigned"
n_bits "W"
bin_pt "0"
quantization "Truncate"
overflow "Wrap"
dbl_ovrd off
use_behavioral_HDL off
pipelined off
use_rpm on
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "addsub"
block_version "8.2.02"
sg_icon_stat "55,71,2,1,white,blue,0,f28631c4"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15 30 34 3"
"8 54 41 29 20 34 20 29 41 54 38 34 30 15 ],[6 16 30 44 54 54 50 54 54 41 53 4"
"4 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 60 60 0 ],[0 58 58 0 "
"0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin "
"icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_"
"label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','te"
"xmode','on');\nfprintf('','COMMENT: end icon text');\n"
Port {
PortNumber 1
Name "n-1"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "AddSub1"
Ports [3, 1]
Position [915, 158, 970, 232]
NamePlacement "alternate"
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
use_carryout off
en on
latency "1"
precision "User Defined"
arith_type "Unsigned"
n_bits "W"
bin_pt "0"
quantization "Truncate"
overflow "Wrap"
dbl_ovrd off
use_behavioral_HDL off
pipelined off
use_rpm on
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "addsub"
block_version "8.2.02"
sg_icon_stat "55,74,3,1,white,blue,0,727db747"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 55 55 0 ],[0 0 74 74 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 3"
"6 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[15 24 37 50 59 59 55 59 59 47 59 "
"50 37 24 15 27 15 15 19 15 15 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 74"
" 74 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: "
"begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black')"
";port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b"
"}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
Port {
PortNumber 1
Name "t1+t3"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "Constant"
Ports [0, 1]
Position [405, 343, 445, 367]
SourceBlock "xbsIndex_r4/Constant"
SourceType "Xilinx Constant Block Block"
arith_type "Signed (2's comp)"
const "1"
n_bits "16"
bin_pt "14"
explicit_period off
period "1"
dsp48_infoedit "The use of this block for DSP48 instructions is"
" deprecated. Please use the Opmode block."
equ "P=C"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
dbl_ovrd off
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "constant"
block_version "8.2.02"
sg_icon_stat "40,24,0,1,white,blue,0,85613821"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 40 40 0 ],[0 0 24 24 ],[0.77 0.82 0.91]);\npatch([14 10 16 10 14 20 22"
" 24 31 26 21 17 23 17 21 26 31 24 22 20 14 ],[3 7 13 19 23 23 21 23 23 18 23 "
"19 13 7 3 8 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 40 40 0 ],[0 24 24 0 0 "
"]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ic"
"on text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: "
"end icon text');\n"
Port {
PortNumber 1
Name "1"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [240, 474, 285, 536]
NamePlacement "alternate"
SourceBlock "xbsIndex_r4/Delay"
SourceType "Xilinx Delay Block"
infoedit "Hardware notes: A delay line is a chain, each l"
"ink of which is an SRL16 followed by a flip-flop. If register retiming is ena"
"bled, the delay line is a chain of flip-flops."
en off
latency "1"
dbl_ovrd off
reg_retiming off
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "20,20,412,256"
block_type "delay"
block_version "8.2.02"
sg_icon_stat "45,62,1,1,white,blue,0,fc531c0e"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 45 45 0 ],[0 0 62 62 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 2"
"8 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[13 20 31 42 49 49 46 49 49 39 49 "
"42 31 20 13 23 13 13 16 13 13 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 62"
" 62 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: "
"begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''"
",'COMMENT: end icon text');\n"
Port {
PortNumber 1
Name "Start_delay1"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [1390, 221, 1445, 269]
SourceBlock "xbsIndex_r4/Delay"
SourceType "Xilinx Delay Block"
infoedit "Hardware notes: A delay line is a chain, each l"
"ink of which is an SRL16 followed by a flip-flop. If register retiming is ena"
"bled, the delay line is a chain of flip-flops."
en off
latency "1"
dbl_ovrd off
reg_retiming off
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "delay"
block_version "8.2.02"
sg_icon_stat "55,48,1,1,white,blue,0,fc531c0e"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 55 55 0 ],[0 0 48 48 ],[0.77 0.82 0.91]);\npatch([15 7 18 7 15 28 31 3"
"4 48 37 27 20 31 20 27 37 48 34 31 28 15 ],[5 13 24 35 43 43 40 43 43 32 42 3"
"5 24 13 6 16 5 5 8 5 5 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 48 48 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i"
"con text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMME"
"NT: end icon text');\n"
}
Block {
BlockType Reference
Name "Delay2"
Ports [1, 1]
Position [595, 422, 630, 468]
NamePlacement "alternate"
SourceBlock "xbsIndex_r4/Delay"
SourceType "Xilinx Delay Block"
infoedit "Hardware notes: A delay line is a chain, each l"
"ink of which is an SRL16 followed by a flip-flop. If register retiming is ena"
"bled, the delay line is a chain of flip-flops."
en off
latency "1"
dbl_ovrd off
reg_retiming off
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "20,20,412,256"
block_type "delay"
block_version "8.2.02"
sg_icon_stat "35,46,1,1,white,blue,0,fc531c0e"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 35 35 0 ],[0 0 46 46 ],[0.77 0.82 0.91]);\npatch([8 2 10 2 8 17 20 23 "
"33 25 18 13 21 13 18 25 33 23 20 17 8 ],[9 15 23 31 37 37 34 37 37 29 36 31 2"
"3 15 10 17 9 9 12 9 9 ],[0.98 0.96 0.92]);\nplot([0 0 35 35 0 ],[0 46 46 0 0 "
"]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ic"
"on text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMEN"
"T: end icon text');\n"
}
Block {
BlockType Reference
Name "Delay3"
Ports [1, 1]
Position [1610, 187, 1640, 213]
SourceBlock "xbsIndex_r4/Delay"
SourceType "Xilinx Delay Block"
infoedit "Hardware notes: A delay line is a chain, each l"
"ink of which is an SRL16 followed by a flip-flop. If register retiming is ena"
"bled, the delay line is a chain of flip-flops."
en off
latency "1"
dbl_ovrd off
reg_retiming off
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "delay"
block_version "8.2.02"
sg_icon_stat "30,26,1,1,white,blue,0,fc531c0e"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 30 30 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([8 4 10 4 8 15 17 19 "
"26 20 14 10 16 10 14 20 26 19 17 15 8 ],[3 7 13 19 23 23 21 23 23 17 23 19 13"
" 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 30 30 0 ],[0 26 26 0 0 ]);\n"
"fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te"
"xt');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en"
"d icon text');\n"
}
Block {
BlockType Reference
Name "Divide1"
Ports [3, 3]
Position [805, 392, 865, 468]
NamePlacement "alternate"
LinkData {
BlockName "D1"
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