vga_gen_46.v

Verilog Vga Generator

// VGA DRIVER,640x480
// INPUT CLOCK=25MHZ
// OUTPUT RGB 2-BIT
module vga_gen_46(clk,h_sync,v_sync,red,green,blue);
//==================================
// base io define
   input clk;
   output h_sync,v_sync;
   output[1:0] red;
   output[1:0] green;
   output[1:0] blue;
   reg h_sync,v_sync;
   reg[1:0] red;
   reg[1:0] green;
   reg[1:0] blue;
// counter register define
// both h&v counter are 10-bit
   reg[9:0] h_conter;
   reg[9:0] v_conter;
// h&v max. value define
   wire h_max=(h_conter==794);
   wire v_max=(v_conter==528);
// BLACK CONTROL
   wire black;
//==================================
// h counter action
   always@(posedge clk)
   if(h_max)
      h_conter<=0;
   else
      h_conter<=h_conter+1;
// v_counter action
   always@(posedge clk)
   if(v_max)
      v_conter<=0;
   else if(h_max)
      v_conter<=v_conter+1;
//====================================
   always@(posedge clk)
   begin
// h_sync action
        h_sync<= ( h_conter<=700);
// v_sync action
        v_sync<= ( v_conter<=526) ;
   end
//=====================================
   always@(posedge clk)
// black control
   if( (h_conter<48)|(h_conter>676)|(v_conter<32)|(v_conter>511) )
      begin
        red[1:0]<=0;
        green[1:0]<=0;
        blue[1:0]<=0;
      end
   else
 /*
 // 显示R G B彩条
      begin
        if(h_conter<=120)    
           begin
           red[1:0]<=3;
           green[1:0]<=0;
           blue[1:0]<=0;
           end
        else if(h_conter<=190)  
           begin
           red[1:0]<=2;
           green[1:0]<=0;
           blue[1:0]<=0;
           end
        else if(h_conter<=260)  
           begin
           red[1:0]<=1;
           green[1:0]<=0;
           blue[1:0]<=0;
           end
        else if(h_conter<=330)
           begin
           red[1:0]<=0;
           green[1:0]<=3;
           blue[1:0]<=0;
           end
        else if(h_conter<=400)
           begin
           red[1:0]<=0;
           green[1:0]<=2;
           blue[1:0]<=0;
           end
        else if(h_conter<=470)
           begin
           red[1:0]<=0;
           green[1:0]<=1;
           blue[1:0]<=0;
           end
        else if(h_conter<=540)
           begin
           red[1:0]<=0;
           green[1:0]<=0;
           blue[1:0]<=3;
           end
        else if(h_conter<=610)
           begin
           red[1:0]<=0;
           green[1:0]<=0;
           blue[1:0]<=2;
           end
        else if(h_conter<=680)
           begin
           red[1:0]<=0;
           green[1:0]<=0;
           blue[1:0]<=1;
           end
      end
*/
/*
// 画1个正方形
      begin
           if( (250<h_conter)&(h_conter<470)&(170<v_conter)&(v_conter<390) )
              begin
              red[1:0]<=1;
              green[1:0]<=3;
              blue[1:0]<=1;
              end
           else
              begin
              red[1:0]<=3;
              green[1:0]<=3;
              blue[1:0]<=3;
              end
*/
// 画3个正方形
      begin
           if( (98<h_conter)&(h_conter<198)&(210<v_conter)&(v_conter<310) )
              begin
              red[1:0]<=3;
              green[1:0]<=0;
              blue[1:0]<=0;
              end
           else if( (312<h_conter)&(h_conter<412)&(210<v_conter)&(v_conter<310) )
              begin
              red[1:0]<=0;
              green[1:0]<=3;
              blue[1:0]<=0;
              end
           else if( (526<h_conter)&(h_conter<626)&(210<v_conter)&(v_conter<310) )
              begin
              red[1:0]<=0;
              green[1:0]<=0;
              blue[1:0]<=3;
              end
           else
              begin
              red[1:0]<=3;
              green[1:0]<=3;
              blue[1:0]<=3;
              end
      end

endmodule