matri_key.map.qmsg

矩阵键盘的扫描的vhdl代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 13 15:40:39 2007 " "Info: Processing started: Thu Dec 13 15:40:39 2007" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Matri_key -c Matri_key " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Matri_key -c Matri_key" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Matri_key.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file Matri_key.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 matrix_key-behave " "Info: Found design unit 1: matrix_key-behave" {  } { { "E:/yys/Matri_key/Matri_key.vhd" "matrix_key-behave" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 matrix_key " "Info: Found entity 1: matrix_key" {  } { { "E:/yys/Matri_key/Matri_key.vhd" "matrix_key" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "division.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file division.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 division-div1 " "Info: Found design unit 1: division-div1" {  } { { "E:/yys/Matri_key/division.vhd" "division-div1" "" { Text "E:/yys/Matri_key/division.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 division " "Info: Found entity 1: division" {  } { { "E:/yys/Matri_key/division.vhd" "division" "" { Text "E:/yys/Matri_key/division.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "line Matri_key.vhd(36) " "Warning: VHDL Process Statement warning at Matri_key.vhd(36): signal line is in statement, but is not in sensitivity list" {  } { { "E:/yys/Matri_key/Matri_key.vhd" "" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "line Matri_key.vhd(44) " "Warning: VHDL Process Statement warning at Matri_key.vhd(44): signal line is in statement, but is not in sensitivity list" {  } { { "E:/yys/Matri_key/Matri_key.vhd" "" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 44 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "line Matri_key.vhd(52) " "Warning: VHDL Process Statement warning at Matri_key.vhd(52): signal line is in statement, but is not in sensitivity list" {  } { { "E:/yys/Matri_key/Matri_key.vhd" "" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 52 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "line Matri_key.vhd(60) " "Warning: VHDL Process Statement warning at Matri_key.vhd(60): signal line is in statement, but is not in sensitivity list" {  } { { "E:/yys/Matri_key/Matri_key.vhd" "" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 60 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "division:U1\|coutQ\[0\]~0 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: division:U1\|coutQ\[0\]~0" {  } { { "E:/yys/Matri_key/division.vhd" "" "coutQ\[0\]~0" { Text "E:/yys/Matri_key/division.vhd" 18 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "c:/quartus/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "c:/quartus/libraries/megafunctions/lpm_counter.tdf" 221 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "alt_counter_f10ke" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 256 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "display\[13\] GND " "Warning: Pin display\[13\] stuck at GND" {  } { { "E:/yys/Matri_key/Matri_key.vhd" "" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 6 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "display\[9\] VCC " "Warning: Pin display\[9\] stuck at VCC" {  } { { "E:/yys/Matri_key/Matri_key.vhd" "" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 6 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "display\[8\] VCC " "Warning: Pin display\[8\] stuck at VCC" {  } { { "E:/yys/Matri_key/Matri_key.vhd" "" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "95 " "Info: Implemented 95 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "72 " "Info: Implemented 72 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 13 15:40:42 2007 " "Info: Processing ended: Thu Dec 13 15:40:42 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}