matri_key.tan.qmsg

矩阵键盘的扫描的vhdl代码

{ "Info" "ITAN_SCC_LOOP" "4 " "Info: Found combinational loop of 4 nodes" { { "Info" "ITAN_SCC_NODE" "i~196 " "Info: Node i~196" {  } {  } 0} { "Info" "ITAN_SCC_NODE" "i~815 " "Info: Node i~815" {  } {  } 0} { "Info" "ITAN_SCC_NODE" "i~192 " "Info: Node i~192" {  } {  } 0} { "Info" "ITAN_SCC_NODE" "i~193 " "Info: Node i~193" {  } {  } 0}  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "i~195 " "Info: Node i~195" {  } {  } 0} { "Info" "ITAN_SCC_NODE" "i~813 " "Info: Node i~813" {  } {  } 0}  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "3 " "Info: Found combinational loop of 3 nodes" { { "Info" "ITAN_SCC_NODE" "i~805 " "Info: Node i~805" {  } {  } 0} { "Info" "ITAN_SCC_NODE" "i~808 " "Info: Node i~808" {  } {  } 0} { "Info" "ITAN_SCC_NODE" "i~809 " "Info: Node i~809" {  } {  } 0}  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "E:/yys/Matri_key/Matri_key.vhd" "" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 5 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTDB_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITDB_RIPPLE_CLK" "division:U1\|clk_outQ " "Info: Detected ripple clock division:U1\|clk_outQ as buffer" {  } { { "E:/yys/Matri_key/division.vhd" "" "" { Text "E:/yys/Matri_key/division.vhd" 18 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "division:U1\|clk_outQ" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[27\] register division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[24\] 55.87 MHz 17.9 ns Internal " "Info: Clock clk has Internal fmax of 55.87 MHz between source register division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[27\] and destination register division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[24\] (period= 17.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.300 ns + Longest register register " "Info: + Longest register to register delay is 14.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[27\] 1 REG LC4_C20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C20; Fanout = 3; REG Node = 'division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[27\]'" {  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "" { division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[27] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 3.900 ns division:U1\|i~309 2 COMB LC6_C13 1 " "Info: 2: + IC(2.200 ns) + CELL(1.700 ns) = 3.900 ns; Loc. = LC6_C13; Fanout = 1; COMB Node = 'division:U1\|i~309'" {  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "3.900 ns" { division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[27] division:U1|i~309 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 5.400 ns division:U1\|i~317 3 COMB LC7_C13 1 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 5.400 ns; Loc. = LC7_C13; Fanout = 1; COMB Node = 'division:U1\|i~317'" {  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "1.500 ns" { division:U1|i~309 division:U1|i~317 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 9.900 ns division:U1\|i~0 4 COMB LC7_C15 34 " "Info: 4: + IC(2.200 ns) + CELL(2.300 ns) = 9.900 ns; Loc. = LC7_C15; Fanout = 34; COMB Node = 'division:U1\|i~0'" {  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "4.500 ns" { division:U1|i~317 division:U1|i~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.700 ns) 14.300 ns division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[24\] 5 REG LC1_C20 3 " "Info: 5: + IC(2.700 ns) + CELL(1.700 ns) = 14.300 ns; Loc. = LC1_C20; Fanout = 3; REG Node = 'division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[24\]'" {  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "4.400 ns" { division:U1|i~0 division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[24] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 50.35 % " "Info: Total cell delay = 7.200 ns ( 50.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns 49.65 % " "Info: Total interconnect delay = 7.100 ns ( 49.65 % )" {  } {  } 0}  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "14.300 ns" { division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[27] division:U1|i~309 division:U1|i~317 division:U1|i~0 division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[24] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK Pin_42 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 34; CLK Node = 'clk'" {  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/yys/Matri_key/Matri_key.vhd" "" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[24\] 2 REG LC1_C20 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C20; Fanout = 3; REG Node = 'division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[24\]'" {  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "2.500 ns" { clk division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[24] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "5.300 ns" { clk division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[24] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK Pin_42 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 34; CLK Node = 'clk'" {  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/yys/Matri_key/Matri_key.vhd" "" "" { Text "E:/yys/Matri_key/Matri_key.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[27\] 2 REG LC4_C20 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_C20; Fanout = 3; REG Node = 'division:U1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[27\]'" {  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "2.500 ns" { clk division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[27] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "5.300 ns" { clk division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[27] } "NODE_NAME" } } }  } 0}  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "5.300 ns" { clk division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[24] } "NODE_NAME" } } } { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "5.300 ns" { clk division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[27] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0}  } { { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "14.300 ns" { division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[27] division:U1|i~309 division:U1|i~317 division:U1|i~0 division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[24] } "NODE_NAME" } } } { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "5.300 ns" { clk division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[24] } "NODE_NAME" } } } { "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" "" "" { Report "E:/yys/Matri_key/db/Matri_key_cmp.qrpt" Compiler "Matri_key" "UNKNOWN" "V1" "E:/yys/Matri_key/db/Matri_key.quartus_db" { Floorplan "" "" "5.300 ns" { clk division:U1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[27] } "NODE_NAME" } } }  } 0}