matri_key.vhd

矩阵键盘的扫描的vhdl代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity matrix_key is
	port(clk : in std_logic;
		 display : out std_logic_vector(13 downto 0);
		 row : buffer std_logic_vector(3 downto 0);----行线 
		 line : in std_logic_vector(3 downto 0));--列线 
end entity matrix_key;
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architecture behave of matrix_key is
component division is
generic (data : integer:=10);
	port(clk_in : in std_logic;
		 clk_out : out std_logic);
end component;
signal read_data : std_logic_vector(3 downto 0);
signal scan_data : std_logic_vector(1 downto 0);
signal clk_temp : std_logic;
	begin
U1: division port map(clk,clk_temp);
P1: process(clk_temp)
	variable temp : std_logic_vector(1 downto 0);
	begin
  	 if clk_temp'event and clk_temp='1' then
		if temp < 3 then temp := temp + 1;
		else temp := (others => '0');
		end if;
	end if;
	scan_data <= temp;
	end process;

P2: process(clk_temp,scan_data)----------扫描
	begin
	 if scan_data="00" then row <= "0001";
		case line is
			when "0001" => read_data <= "0000";
			when "0010" => read_data <= "0001";
			when "0100" => read_data <= "0010";
			when "1000" => read_data <= "0011";
			when others => null;
	    end case;
	elsif scan_data="01" then row <= "0010";
		  case line is
			when "0001" => read_data <= "0100";
			when "0010" => read_data <= "0101";
			when "0100" => read_data <= "0110";
			when "1000" => read_data <= "0111";
			when others => null;
	    end case;
	elsif scan_data="10" then row <= "0100";
		case line is
			when "0001" => read_data <= "1000";
			when "0010" => read_data <= "1001";
			when "0100" => read_data <= "1010";
			when "1000" => read_data <= "1011";
			when others => null;
	    end case;
	elsif scan_data="11" then row <= "1000";
		case line is
			when "0001" => read_data <= "1100";
			when "0010" => read_data <= "1101";
			when "0100" => read_data <= "1110";
			when "1000" => read_data <= "1111";
			when others => null;
	    end case;
	else null;
	end if;
	end process;
P3: process(clk_temp,scan_data,read_data)-------译码
		begin
		case read_data is
		when "0000"	=> display <= "01111110000110";---01
		when "0001"	=> display <= "01111111011011";---02
		when "0010"	=> display <= "01111111001111";---03
		when "0011"	=> display <= "01111111100110";---04
		when "0100"	=> display <= "01111111101101";---05
		when "0101"	=> display <= "01111111111101";---06
		when "0110"	=> display <= "01111110000111";---07
		when "0111"	=> display <= "01111111111111";---08
		when "1000"	=> display <= "01111111101111";---09
		when "1001"	=> display <= "00001100111111";---10
		when "1010"	=> display <= "00001100000110";---11
		when "1011"	=> display <= "00001101011011";---12
		when "1100"	=> display <= "00001101001111";---13
		when "1101"	=> display <= "00001101100110";---14
		when "1110"	=> display <= "00001101101101";---15
		when "1111"	=> display <= "00001101111101";---16
		end case;
	end process;
end architecture;