decoder7s.vhd

来自「一个用vhdl写的时钟代码」· VHDL 代码 · 共 29 行

-----------------------7段数码管译码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
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entity decoder7s is
	port(binary : in std_logic_vector(3 downto 0);
	     bcd : out std_logic_vector(6 downto 0));
end entity decoder7s;
-------------------------
architecture behave of decoder7s is
 begin
  process(binary)
   begin
	case binary is
		when "0000" => bcd <= "0111111";--0
		when "0001" => bcd <= "0000110";--1
		when "0010" => bcd <= "1011011";--2
		when "0011" => bcd <= "1001111";--3
		when "0100" => bcd <= "1100110";--4
		when "0101" => bcd <= "1101101";--5
		when "0110" => bcd <= "1111101";--6
		when "0111" => bcd <= "0000111";--7
		when "1000" => bcd <= "1111111";--8
		when "1001" => bcd <= "1101111";--9
		when others => null;
  end case;
end process;
end architecture behave;